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Entering Resource AssignmentsThe MAX+PLUS
Design Architect SchematicsIn Design Architect schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:
Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example4/fa2, which includes resource assignments.
For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. Go to Modifying the Assignment & Configuration File with the setacf Utility for more information.
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||||||