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The following topic describes how to use the Exemplar Logic Galileo Extreme software with This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic. Setting Up the MAX+PLUS
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| Go to the following MAX+PLUS II | |
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Go to the following topics, which are available on the web, for additional information: | |
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To use the MAX+PLUS
Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization for information about the MAX+PLUS II/Mentor Graphics directories that are created during MAX+PLUS II installation.
| The information presented here assumes that you are using a C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell. |
To set up your working environment for the MAX+PLUS II/Mentor Graphics interface, follow these steps:
setenv ALT_HOME /usr/maxplus2 | |
setenv MGC_WD <user-specified working directory> | |
setenv MGC_HOME <Mentor Graphics system directory> | |
setenv MAX2_MENTOR /usr/maxplus2/mentor/max2 | |
setenv MGC_LOCATION_MAP <user-specified location_map file> | |
setenv EXEMPLAR <Galileo or Leonardo system directory> |
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Installing the |
PATH environment variable in your .cshrc file, where <os> is the operating system, e.g., SUN4 for SunOS; SUN5 for Solaris.
setenv MAX2_QSIM /usr/maxplus2/simlib/mentor/max2sim |
source ~/.cshrc at a UNIX prompt to source the .cshrc file and validate the settings in steps 1 through 4.$MAX2_MENTOR | |
/usr/maxplus2/mentor/max2 | |
$MGC_GENLIB | |
/<user-specified Mentor Graphics GEN_LIB directory> | |
$MGC_LSLIB | |
/<user-specified Mentor Graphics LS_LIB directory> | |
$MAX2_EXAMPLES | |
/<user-specified example directory> | |
$MAX2_LMCLIB | |
/<user-specified Logic Modeling directory> | |
$MAX2_GENLIB | |
/usr/maxplus2/simlib/mentor/alt_max2 | |
$MAX2_QSIM | |
/usr/maxplus2/simlib/mentor/max2sim | |
$MAX2_FONT | |
/usr/maxplus2/mentor/max2/fonts | |
$MGC_SYS1076_STD | |
/<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ std | |
$MGC_SYS1076_ARITHMETIC | |
/<user-specified MGC_HOME directory>/pkgs/sys_1076_std/arithmetic | |
$MGC_SYS1076_PORTABLE | |
/<user-specified MGC_HOME directory>/pkgs/sys_1076_std/mgc_portable | |
$MGC_SYS1076_IEEE | |
/<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ieee | |
$MGC_SYS1076_SRC | |
/<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ src | |
$MAX2_MFLIB | |
/usr/maxplus2/simlib/mentor/alt_mf |
| Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/location_map/location_map file. |
[library] section of your quickhdl.ini file: altera = $MAX2_MFLIB.
$MAX2_VTLLIB | |
/usr/maxplus2/simlib/mentor/alt_vtl |
cp /usr/maxplus2/maxplus2.ini $HOME | |
chmod u+w $HOME/maxplus2.ini |
| The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as Alteraprovided logic and symbol library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory. Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information. |
| Go to the following topics, which are available on the web, for additional information: | |
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The following products are used to generate, process, synthesize, and verify a project with the MAX+PLUS
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Mentor Graphics
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Exemplar
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Altera
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| The MAX+PLUS II read.me file provides up-to-date information on which versions of Mentor Graphics applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu. |
The MAX+PLUS
| You can create your own libraries of custom functions for use in Design Architect schematics and VHDL and Verilog HDL design files. You can use custom functions to incorporate an EDIF Input File (.edf), Text Design File (.tdf), or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the |
You can enter a Design Architect schematic with logic functions from these Altera-provided symbol libraries: ALTERA LPMLIB, ALTERA GENLIB, LSTTL BY TYPE, and LSTTL ALL PARTS. You can access these libraries by choosing Altera Libraries (Libraries menu) in the Design Architect software. For information on using library of parameterized modules (LPM) functions, see ALTERA LPMLIB Library below.
The ALTERA GENLIB symbol library (called the Altera library for VHDL) includes several MAX+PLUS II primitives for controlling design synthesis and fitting. It also includes four macrofunctions (8count, 8mcomp, 8fadd, and 81mux) that are optimized for different Altera device families, and the clklock phase-locked loop megafunction, which is supported for some FLEX
The following table shows the MAX+PLUS II-specific logic functions.
| Table 1. MAX+PLUS II-Specific Logic Functions | |||||
8fadd |
8-bit full adder | LCELL |
Logic cell buffer | EXP |
MAX |
8mcomp |
8-bit magnitude comparator | GLOBAL |
Global input buffer | SOFT |
Soft buffer |
8count |
8-bit up/down counter | CASCADE |
FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer | OPNDRN |
Open-drain buffer |
81mux |
8-to-1 multiplexer | CARRY |
FLEX 6000, FLEX 8000, and FLEX 10K carry buffer | DFFE DFFE6KNote (2) |
D-type flipflop with Clock Enable |
clklock |
Phase-locked loop | ||||
Notes:
a_" in VHDL designs. For example, 8fadd must be specified as a_8fadd instead.DFFE primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the DFFE6K primitive.
| Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions. |
The Alteraprovided ALTERA LPMLIB library, which is available for Design Architect schematics and VHDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. The LPM standard defines a set of parameterized modules (i.e., parameterized functions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family. The parameters you specify for each LPM function determine which simulation models are generated.
| Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions. |
Go to the following topics, which are available on the web, for additional information: | |
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Design Architect software automatically creates and maintains the project directory structure required for all stages of design entry. Galileo Extreme, Leonardo, and ENWrite software create a max2 subdirectory, if it does not already exist, under the project directory. These software applications also generate EDIF netlist files, and copy them from the <project name> directory to this max2 subdirectory. All MAX+PLUS
Simulation files created with Mentor Graphics applications and Logic Modeling files are located in the board-level simulation subdirectory of the project directory. You can use these files during simulation with QuickSim II software.
The only directory you need to create is the local work directory, which should contain all project directories. Figure 1 shows the recommended file structure.
Go to the following MAX+PLUS II
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Design Architect software generates the following files for each schematic:
The files generated for each schematic are stored in the schematic's <drawing name> directory and should not be edited. Mentor Graphics software automatically manages file storage and retrieval operations through this <drawing name> directory structure, which does not reflect hierarchical design relationships. Figure 1 shows a sample file structure with project1 as the UNIX project directory, and design1, subdesign1, and subdesign2 as the directories for the top-level design and subdesigns of the project.
Figure 1. Design Architect Project File Structure
When the ENWrite utility converts the schematic into an EDIF netlist file, it processes the design information and all related file subdirectories, then creates the EDIF netlist file in the directory defined by the user. The EDIF netlist file is named <project name>.edf, where <project name> is the name of the top-level design file. The <project name>.edf file is automatically moved to the max2 directory under the project directory.
| Go to the following MAX+PLUS II | |
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In the MAX+PLUS
Figure 1. Sample MAX+PLUS II Project Directory
The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.
Go to the following MAX+PLUS II
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The following table shows the MAX+PLUS
| For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual. |
| Table 1. MAX+PLUS II Directory Organization | |
| .lmf | Contains the Altera-provided Library Mapping Files, mnt8_bas.lmf and exemplar.lmf, that map Mentor Graphics and Exemplar Logic logic functions to equivalent MAX+PLUS II logic functions. |
| ./mentor | Contains the AMPLE userware for the MAX+PLUS II/Mentor Graphics interface. |
| ./simlib/mentor/alt_max2 | Contains MAX+PLUS II primitives such as CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE, and DFFE6K (D flipflop with Clock Enable) for use in Design Architect schematics. |
| ./simlib/mentor/max2sim | Contains the MAX+PLUS II/Mentor Graphics simulation model library, max2sim, for use with QuickSim II and QuickPath software. |
| ./simlib/mentor/synlib | Contains the MAX+PLUS II synthesis library for use with AutoLogic II software, which supports synthesis for users running Mentor Graphics version B1. |
| ./simlib/mentor/alt_mf | Contains the MAX+PLUS II macrofunction and megafunction libraries. |
| ./simlib/mentor/alt_vtl | Contains the MAX+PLUS II VITAL library. |
The following figure shows the design entry flow for the
| Alteraprovided items are shown in blue. |
You can create VHDL and Verilog HDL design files with the MAX+PLUS
The MAX+PLUS II Text Editor offers the following advantages:
Templates are available with the VHDL Templates and Verilog Templates commands (Template menu). These templates are also available in the ASCII vhdl.tmp and verilog.tmp files, respectively, which are located in the /usr/maxplus2 directory.
If you use the MAX+PLUS II Text Editor to create your VHDL design, you can turn on the Syntax Coloring command (Options menu). The Syntax Coloring feature displays keywords and other elements of text in text files in different colors to distinguish them from other forms of syntax.
To create a VHDL or Verilog HDL design file for use with the MAX+PLUS II software, go through the following steps:
Enter a VHDL or Verilog HDL design in the MAX+PLUS II Text Editor or another standard text editor and save it in your working directory.
Enter primitives, macrofunctions, and megafunctions in your VHDL or Verilog HDL design from the Altera library.
The following topics describe special steps needed to instantiate LPM and clklock functions:
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You can instantiate MegaCore functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPP). The OpenCore feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support. |
(Optional) Use the QuickHDL software to functionally simulate the design file, as described in Performing a Functional Simulation with QuickHDL Software and Performing a Functional Simulation with QuickHDL Pro Software.
Once you have created a VHDL or Verilog HDL design, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:
You can synthesize and optimize your design and create an EDIF netlist file, as described in Synthesizing & Optimizing VHDL & Verilog HDL Projects with Galileo Extreme Software or Synthesizing & Optimizing VHDL & Verilog HDL Projects with Leonardo Software.
You can use the Altera VHDL Express utility, vhd_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with QuickHDL software, as described in Using the Altera Schematic Express (vhd_exprss) Utility.
Installing the Alteraprovided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample VHDL design files:
| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II |
After you have created a VHDL or Verilog HDL design, you can use Exemplar Logic's Galileo Extreme software to synthesize and optimize your VHDL Design File (.vhd) or Verilog Design File (.v) and prepare it for compilation with the MAX+PLUS
To synthesize and optimize your project and generate an EDIF netlist file with Galileo Extreme software, go through the following steps:
max2_galileo
Installing the
| Go to the following MAX+PLUS II | |
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The
| Refer to the following sources for additional information: | |
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To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:
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Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information. |
You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type setacf -h maxplus2 -h |
| If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6. |
VCC or GND for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.
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This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF. |
The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).
| See step 3 for information on running MAX+PLUS II software from the command line. |
The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:
| Refer to the following sources for additional information: | |
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Go to the following topics, which are available on the web, for additional information: | |
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Once you have successfully compiled and simulated a project with the
Altera-provided items are shown in blue. |
You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.
Table 1. Altera Programming Hardware |
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Hardware Option |
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Work- stations |
ACEX® 1K
Devices |
MAX® 3000A
Devices |
& MAX 5000 Devices |
& MAX 7000E Devices |
MAX 7000A, |
FLEX 6000A, FLEX 8000, FLEX 10K, FLEX 10KA, FLEX 10KB, & FLEX 10KE Devices |
Programming/ Configuration |
| Logic Programmer card, PL-MPU Master Programming Unit, and device-specific adapters |
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If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.
Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.
| Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files. |
Go to the following topics, which are available on the web, for additional information: | |
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Copyright © 1995-2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.