Table 1 shows the command-line syntax for using Powerview functions.
| Action |
Command |
| Start VHDL Analyzer software |
vhdl -v <project name> |
| Start ViewSynthesis software |
vhdldes |
| Load Altera® technology library |
vhdldes> technology altera |
| Compile a VHDL design |
vhdldes> vhdl <project name> |
| Synthesize a design |
vhdldes> synthesize |
| Generate wirelist file |
vhdldes> wir |
| Create a schematic representation |
vhdldes> viewgen |
| Generate a synthesis report file |
vhdldes> report |
| Start the graphical user interface for ViewSynthesis |
vhdldes> vdesgui |
| Start the VHDL-to-symbol utility |
vhdl2sym <project name> |
| Start vsm |
vsm <project name> |
| Start ViewSim simulator |
viewsim <project name> -<project name>.cmd |
| Start edifneto |
edifneto -f <project name>-l (std or altera) <project name>.edf |
| Start Vantage VHDL Analyzer software |
analyze -src <design file> |
| Start MOTIVE for Powerview software |
mfp |