MAX+PLUS II ACCESS Key Guidelines
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Assigning a Device & Clock Frequency (fMAX)

You can specify the desired Clock frequency (called fMAX in the MAX+PLUS® II software) and the target device family before synthesizing and optimizing the design with the FPGA Express software. You can optionally select a specific device and speed grade within the target device family. These assignments are stored in the design's Assignment & Configuration File, <design name>.acf, which is generated automatically by the FPGA Express software.

To assign a device or device family and the Clock frequency, follow these steps:

  1. If you have not already done so, identify the top-level design for your project from the Design Sources window. Select the top-level design from the Top-Level Design drop-down list on the toolbar. The Create Implementation dialog box is displayed.

  2. Enter an implementation name in the Implementation Name box. If you do not enter a name, FPGA Express software automatically creates a unique implementation name.

  3. Select Altera from the Vendor list.

  4. Select the appropriate Altera device family from the Family list.

  5. (Optional) Select a specific device from the Device list, and select a specific speed grade from the Speed Grade list.

  6. Type the desired Clock frequency in the Clock Frequency text box. This Clock frequency is used as the default value for all Clock signals in the design.

  7. (Optional) Select speed/area and CPU effort settings, as described in Specifying the Speed/Area & CPU Effort Settings with the FPGA Express Software.

  8. Continue with the steps necessary to process your design, as described in Synthesizing & Optimizing VHDL or Verilog HDL Files with FPGA Express Software.

Note: You can also edit the Clock frequency by double-clicking on the design implementation name to open the constraint tables and entering information on the Clock tab. For more information, refer to Assigning Pins, Logic Options, and tSU, tCO & tPD Timing Constraints.

Go to:

Go to the following sources for related information:

  • FPGA Express Help
  • "Guidelines for Achieving Maximum Speed Performance" in MAX+PLUS II Help

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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