![]() |
|||||||
|
|
|||||||
Assigning PinsYou can assign a single port to a specific pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. You can specify pins in VHDL or Verilog HDL designs, or in a Synplify Design Constraints File (.sdc). If you add timing constraints or resource assignments in a separate Synplify Design Constraints File (.sdc), you must add the Synplify Design Constraints File (.sdc) to the project by adding it to the Source Files list in the Synplify window.
VHDL SyntaxUse the following syntax to assign a pin in VHDL:
Example: attribute altera_chip_pin_lc : string; attribute altera_chip_pin_lc of result : signal is "@17, @166, @191, @152, @15, @148, @147, @149"; Verilog HDL SyntaxUse the following syntax to assign a pin in Verilog HDL: <port name> Example: output [7:0] sum /* synthesis altera_chip_pin_lc="@17, @166, @191, @152, \ @15, @148, @147, @149" */; Synplify Design Constraints File SyntaxUse the following syntax to assign a pin in a Synplify Design Constraints file:
Example:
define_attribute {DATA0[7:0]} altera_chip_pin_lc "@115,@116,@117,
@118,@119,@120,@121,@122"
|
|||||||
| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||||
|
| |||||||
|
Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||||||