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Project Simulation FlowFigure 1 shows the project simulation flow for the Figure 1. MAX+PLUS II/Synopsys Project Simulation Flow
The MAX+PLUS II/Synopsys design environment fully supports design verification with the Synopsys VHDL System Simulator (VSS). For pre-route simulation, you can simulate a design that has been compiled with one of the Synopsys compilers. For post-route simulation, you can simulate the VHDL Output File (.vho) that |
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||