MAX+PLUS II ACCESS Key Guidelines
List by VendorList by ToolList by FunctionCadence Topicsblank

Performing a Functional Simulation of a Composer Schematic with Verilog-XL Software

You can perform a functional simulation of a Cadence Composer schematic with the Verilog-XL simulator before compiling your project with the MAX+PLUS® II software.

To functionally simulate a Composer schematic, follow these steps:

  1. Be sure to set up your working environment correctly, as described in Setting Up the
    MAX+PLUS II/Cadence Working Environment
    .

  2. Create a Composer schematic and save it in your working directory, as described in Creating Composer Schematics for Use with MAX+PLUS II Software.

  3. In Composer, select Simulation from the Tools drop-down list.

  4. Select Verilog-XL to start the Verilog-XL Integration Control window.

  5. When you are ready to compile the project, generate an EDIF netlist file <design name>.edf with the altout utility, as described in Converting Composer Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the altout Utility.

  6. Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
border line
| Home | List by Vendor | List by Tool | List by Function | Cadence Topics |
Documentation Conventions

Copyright © 1995-2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice.