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Setting Up the DesignWare Interface

The DesignWare interface synthesizes FLEX® 6000, FLEX 8000 and FLEX 10K designs by operator inference. It replaces the HDL operators +, -, >, <, >=, and <= with FLEX-optimized design implementations.

Altera provides DesignWare Synthetic Libraries that are pre-compiled for the current version of Synopsys tools. These library files are located in the /usr/maxplus2/synopsys/library/alt_syn/<device family>/lib directory.

To use the DesignWare interface with FLEX 6000, FLEX 8000 and FLEX 10K devices, follow these steps:

  1. Add synthetic_library and define_design_lib parameters to your .synopsys_dc.setup configuration file and modify the link_library parameter as shown in Table 1 or Table 2.

    Table 1. DesignWare Parameters to Add to the .synopsys_dc.setup File for the Design Compiler Software
    Device Family
    Parameters to Add to the .synopsys_dc.setup File
    FLEX 6000 synthetic_library = {flex6000<speed grade>.sldb}; Enter
    link_library = {flex6000
    <speed grade>.sldb flex6000<speed grade>.db}; Enter
    define_design_lib DW_FLEX6000<speed grade> -path /usr/maxplus2/synopsys/library/alt_syn/flex6000/lib/
    dw_flex6000
    <speed grade> Enter
    FLEX 8000 synthetic_library = {flex8000[<speed grade>].sldb};  Enter
    link_library = {flex8000[
    <speed grade>].sldb flex8000[<speed grade>].db}; Enter
    define_design_lib DW_FLEX8000[
    <speed grade>] -path /usr/maxplus2/synopsys/library/alt_syn/flex8000
    /lib/dw_flex8000[
    <speed grade>] Enter
    FLEX 10K synthetic_library = {flex10k[<speed grade >].sldb}; Enter
    link_library = {flex10k[
    <speed grade>].sldb flex10k[<speed grade>].db}; Enter
    define_design_lib DW_FLEX10k[
    <speed grade>] -path /usr/maxplus2/synopsys/library/alt_syn/flex10k/lib
    /dw_flex10k[
    <speed grade>] Enter


    Table 2. DesignWare Parameters to Add to the .synopsys_dc.setup File for the FPGA Compiler Software
    Device Family
    Parameters to Add to the .synopsys_dc.setup File
    FLEX 6000 synthetic_library = {flex6000
    <speed grade>_fpga.sldb}; Enter
    link_library = {flex6000
    <speed grade>_fpga.sldb flex6000<speed grade>_fpga.db}; Enter
    define_design_lib DW_FLEX6000<speed grade>_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex6000
    /lib/dw_flex6000
    <speed grade>_fpga Enter
    FLEX 8000 synthetic_library = {flex8000[<speed grade>]_fpga.sldb}; Enter
    link_library = {flex8000[
    <speed grade>]_fpga.sldb flex8000[<speed grade>]_fpga.db}; Enter
    define_design_lib DW_FLEX8000[
    <speed grade>]_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex8000/lib /dw_flex8000[<speed grade>]_fpga Enter
    FLEX 10K synthetic_library = {flex10k[<speed grade>]_fpga.sldb}; Enter
    link_library = {flex10k[
    <speed grade>]_fpga.sldb flex10k[<speed grade>]_fpga.db}; Enter
    define_design_lib DW_FLEX10k[
    <speed grade>]_FPGA -path /usr/maxplus2/synopsys/library/alt_syn/flex10k/lib /dw_flex10k[<speed grade>]_fpga Enter

  2. Specify the libraries listed in Table 3 as your synthetic library and as the first of your link libraries.

    For FLEX 6000 devices, you must specify either -2 or -3 for the <speed grade> variable. For FLEX 8000 and FLEX 10K devices, you can specify -2, -3, -4, -5, or -6; or -2, -3, -4, or -5; respectively, for the <speed grade> variable. If you do not specify a speed grade for FLEX 8000 or FLEX 10K devices, the MAX+PLUS® II software selects the fastest device in the specified family as the target device.

    Table 3. FLEX 6000, FLEX 8000 & FLEX 10K DesignWare Synthetic Libraries
    Altera® Device Family Synopsys Design Compiler Synopsys FPGA Compiler
    FLEX 6000
    Synthetic Library
    flex6000-2.sldb
    flex6000-3.sldb
    flex6000-2_fpga.sldb
    flex6000-3_fpga.sldb
    FLEX 8000
    Synthetic Library
    flex8000.sldb
    flex8000-2.sldb
    flex8000-3.sldb
    flex8000-4.sldb
    flex8000-5.sldb
    flex8000-6.sldb
    flex8000_fpga.sldb
    flex8000-2_fpga.sldb
    flex8000-3_fpga.sldb
    flex8000-4_fpga.sldb
    flex8000-5_fpga.sldb
    flex8000-6_fpga.sldb
    FLEX 10K
    Synthetic Library
    flex10k.sldb
    flex10k-2.sldb
    flex10k-3.sldb
    flex10k-4.sldb
    flex10k-5.sldb
    flex10k_fpga.sldb
    flex10k-2_fpga.sldb
    flex10k-3_fpga.sldb
    flex10k-4_fpga.sldb
    flex10k-5_fpga.sldb

  3. If necessary, compile the DesignWare libraries, as described in Updating DesignWare Libraries. Altera provides pre-compiled DesignWare libraries, as described above. However, Altera also provides compatible source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare with any version of the Design Compiler. They also allow you to install components whose source is written in VHDL, even if you are licensed only for the HDL Compiler for Verilog.

Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information:

 

Go to the following topics, which are available on the web, for additional information:

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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