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Instantiating LPM Functions in VHDL

You can enter library of parameterized modules (LPM) functions in your VHDL design. The MAX+PLUS® II software supports all LPM functions except the truth table, finite state machine, and pad functions. The FPGA Express software supports all LPM functions that are supported in the MAX+PLUS II software except the lpm_and, lpm_or, lpm_xor, and lpm_mux functions. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on all LPM functions.

To instantiate an LPM function in a VHDL design, follow these steps:

  1. Create an instance of an LPM function in VHDL with a Component Instantiation Statement. VHDL Component Declarations for LPM functions are available in MAX+PLUS II Help and also installed automatically in the following FPGA Express directory:

    <drive>:\synopsys\fpga_express\lib\packages\lpm\lpm_components.vhd

    Use named association to specify parameter values in the Generic Map Clauses of LPM function instantiations. Figure 1 shows the Component Declaration for the lpm_ram_dq function.

    Figure 1. Component Declaration for lpm_ram_dq (from lpm_components.vhd)

    COMPONENT lpm_ram_dq
       GENERIC (
                LPM_WIDTH: POSITIVE;
                LPM_TYPE : STRING := L_RAM_DQ;
                LPM_WIDTHAD: POSITIVE;
                LPM_NUMWORDS: STRING := UNUSED;
                LPM_FILE: STRING := UNUSED;
                LPM_INDATA: STRING := REGISTERED;
                LPM_ADDRESS_CONTROL : STRING := REGISTERED;
                LPM_OUTDATA: STRING := REGISTERED
                );
       PORT    (
                data     : IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
                we       : IN STD_LOGIC := '1';
                inclock  : IN STD_LOGIC := '1';
                outclock : IN STD_LOGIC := '1';
                address  : IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
                q        : OUT STD_LOGIC_VECTOR (LPM_WIDTH-1 DOWNTO 0)
               );
    END COMPONENT;
    

  2. Manually tie any pins that require an initial value of logic 1 to vcc. The FPGA Express software does not support initial values of logic 1 in Component Declarations. However, it does support initial values of logic 0.

    Figure 2 shows an example of instantiating an lpm_ram_dq function in VHDL.

    Figure 2. VHDL Design File with lpm_ram_dq Instantiation

    LIBRARY ieee;
    USE ieee.std_logic_1164.all;
    LIBRARY lpm;
    USE lpm.lpm_components.all;
    
    ENTITY design IS
       PORT(
            din  : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
            we   : IN STD_LOGIC;
            clk  : IN STD_LOGIC;
            addr : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
            dat  : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
            );
    END design;
    
    ARCHITECTURE struct OF design IS
       SIGNAL vcc : STD_LOGIC;
    
    BEGIN  --  struct
       vcc <= '1';
    
    u1:  lpm_ram_dq
       GENERIC MAP(
                   LPM_WIDTH   => 16,
                   LPM_WIDTHAD => 4,
                   LPM_INDATA  => "UNREGISTERED",
                   LPM_OUTDATA => "UNREGISTERED"
                  )
    
       PORT MAP(
                data     => din,
                address  => addr,
                we       => we,
                q        => dat,
                inclock  => vcc,
                outclock => clk
                );
    END struct;

  3. Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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