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MAX+PLUS II Architecture Control Logic Function Instantiation Example for Verilog HDLYou can instantiate Figure 1 shows an example of an 8-bit counter that is instantiated using the Figure 1. Sample Verilog HDL File with Logic Function Instantiation (counter.v)
module counter (clock, ena, load, dnup, set, clear, i, q, cout);
output cout;
output[7:0] q;
input[7:0] i;
input clock, ena, load, dnup, set, clear;
A_8COUNT u1 (.A(i[0]), .B(i[1]), .C(i[2]), .D(i[3]),
.E(i[4]), .F(i[5]), .G(i[6]), .H(i[7]),
.LDN(load), .GN(ena), .DNUP(dnup), .SETN(set),
.CLRN(clear), .CLK(clock), .QA(q[0]), .QB(q[1]),
.QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]),
.QG(q[6]), .QH(q[7]), .COUT(cout) );
endmodule
The sample file shown in Figure 1 can be synthesized with the Design Compiler or FPGA Compiler. You can also simulate it with the Cadence Verilog-XL Simulator by typing the following command at the dc_shell prompt:
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |
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