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The following topics describe how to use the Synopsys Design Compiler and FPGA Compiler software with the This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic. Setting Up the MAX+PLUS II/Synopsys Working Environment
Design Entry
Synthesis & Optimization
Setting Up the MAX+PLUS II/Synopsys Working EnvironmentTo use the
To set up your working environment for the MAX+PLUS II/Synopsys interface, follow these steps:
MAX+PLUS II/Synopsys Software RequirementsThe following applications are used
to generate, process, synthesize, and verify a project with
Compilation with the Synopsys Design Compiler and FPGA Compiler is available only on Sun SPARCstations running Solaris 2.4 or higher.
Setting Up Design Compiler & FPGA Compiler Configuration FilesThe .synopsys_dc.setup configuration file allows you to set both Design Compiler and FPGA Compiler variables. The compilers read .synopsys_dc.setup files from three directories, in the following order:
The most recently read configuration file has highest priority. For example, a configuration file in the directory where you start the Design Compiler or FPGA Compiler software has priority over the other configuration files, and a configuration file in the home directory has priority over a configuration file in the root directory. To set up your configuration files, follow these steps:
Setting Up the DesignWare InterfaceThe DesignWare interface synthesizes Altera provides DesignWare Synthetic Libraries that are pre-compiled for the current version of Synopsys tools. These library files are located in the /usr/maxplus2/synopsys/library/alt_syn/<device family>/lib directory. To use the DesignWare interface with FLEX 6000, FLEX 8000 and FLEX 10K devices, follow these steps:
Updating DesignWare LibrariesAlthough Altera provides DesignWare libraries that are pre-compiled for the current version of Synopsys tools, you may wish to recompile the libraries. Altera provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare software with any version of the Design Compiler or FPGA Compiler software.They also allow you to install components whose source is written in VHDL, even if you are licensed only for the Verilog HDL Compiler software. Source files for the Design Compiler software are automatically installed in the following directories:
Source files for the FPGA Compiler are automatically installed in the following directories:
You can compile the VHDL source file
for use with the appropriate library. Refer to Table 1 to
determine which commands you should type at the UNIX prompt to
compile the library.
Notes:
Design Compiler & FPGA Compiler Technology LibrariesThe Altera recommends instantiating these functions directly in your designs only if the Synopsys compilers do not appear to recognize the functions when synthesizing your design, or if you prefer to hand-optimize certain portions of your design.
Table 2 lists the technology library names.
Altera VHDL & Verilog HDL alt_mf Logic Function LibraryThe alt_mf library contains behavioral VHDL and Verilog HDL models of the
The behavioral descriptions of these four functions are contained in the /usr/maxplus2/synopsys/library/alt_mf/src directory, which contains the following files:
If you wish to simulate a VHDL design containing these logic functions, you can use the Altera-provided shell script analyze_vss to create a design library called altera. This library allows you to reference the functions through the VHDL Library and Use Clauses, which direct the Design Compiler or FPGA Compiler software to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library by analyzing the VHDL System Simulator (VSS) simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting Up VSS Configuration Files for more information on using the analyze_vss shell script. Complete VHDL and Verilog HDL behavioral descriptions of these logic functions are included in the mf.vhd and mf.v files so that you can optionally retarget your design to other technology libraries.
Altera DesignWare FLEX 6000, FLEX 8000 & FLEX 10K Synthetic LibrariesThe The Altera DesignWare interface for FLEX devices offers three major advantages to Synopsys designers:
Table 1 lists the Altera DesignWare synthetic libraries for FLEX 6000, FLEX 8000, and FLEX 10K devices.
Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries. Refer to DesignWare FLEX 8000 Synthesis Example for an example showing how DesignWare synthesis affects design processing.
Altera Post-Synthesis LibrariesThe /usr/maxplus2/synopsys/library/alt_post/syn/lib directory contains the post-synthesis library for technology mapping and timing back-annotation. The
MAX+PLUS II/Synopsys Interface File OrganizationTable 1 shows the
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| Altera-provided items are shown in blue. |
You can create VHDL design files with the
Once you have created a VHDL design, you can use the Design Compiler or FPGA Compiler to synthesize and optimize it, and then generate an EDIF netlist file that can be processed with the MAX+PLUS II software.
To create a VHDL design that can be synthesized and optimized with the Design Compiler or FPGA Compiler, follow these steps:
a_8count, a_8mcomp, a_8fadd, and a_81mux functions. See MAX+PLUS II Architecture Control Logic Function Instantiation Example for VHDL for an example.
DW03_updn_ctr). Go to DesignWare Up/Down Counter Function Instantiation Example for VHDL for an example.
clklock megafunction, which is supported for selected FLEX 10K devices. This function is generated with the gencklk utility. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for instructions.
You can also instantiate any other Altera macrofunction or non-parameterized megafunction, i.e., functions not listed above, for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler or FPGA Compiler. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example.
For information on MAX+PLUS II primitives, megafunctions, and macrofunctions, choose Primitives, Megafunctions/LPM, or Old-Style Macrofunctions from the MAX+PLUS II Help menu. When searching for information on the alt_mf library functions, drop the initial "a_" from the function name.
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| If you instantiate a "black box" logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent MAX+PLUS II function before you compile the project with the MAX+PLUS II software. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example. |
Installing the Altera-provided MAX+PLUS II/Synopsys Logic interface on your computer automatically creates the following VHDL sample files:
| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II | |
You can instantiate the
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Go to the following topics for information and examples of how to instantiate functions that are not considered to be hollow bodies, including functions in the alt_mf library, RAM and ROM, and the
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Unlike other logic functions, MAX+PLUS II primitives do not need to be defined with Component Declarations unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the ATRIBUF and TRIBUF primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."
Figure 1 shows a 4-bit full adder with registered output that also instantiates an AGLOBAL or GLOBAL primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX 7000 architecture. The design uses an old-style 7483 macrofunction, which is represented as a hollow body named fa4.
Figure 1. 4-Bit Adder Design with Registered Output (adder.vhd)
LIBRARY ieee; USE ieee.std_logic_1164.ALL; |
ENTITY adder IS
PORT (a, b : IN STD_LOGIC_VECTOR(4 DOWNTO 1);
clk, rst : IN STD_LOGIC;
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cout : OUT STD_LOGIC;
regsum : OUT STD_LOGIC_VECTOR(4 DOWNTO 1));
END adder;
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ARCHITECTURE MAX7000 OF adder IS |
SIGNAL sum : STD_LOGIC_VECTOR(4 DOWNTO 1); SIGNAL ci, gclk, grst : STD_LOGIC; |
-- Component Declaration for GLOBAL primitive
-- For FLEX devices, global, a_in, and a_out should be replaced with
-- aglobal, in1, and Y, respectively
COMPONENT global
PORT (a_in : IN STD_LOGIC;
a_out : OUT STD_LOGIC);
END COMPONENT;
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-- Component Declaration for fa4 macrofunction
COMPONENT fa4
PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN STD_LOGIC;
s1,s2,s3,s4,c4 : OUT STD_LOGIC);
END COMPONENT;
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BEGIN ci <= '0'; |
-- FA4 Component Instantiation u0: fa4 |
PORT MAP (ci,a(1),b(1),a(2),b(2),a(3),b(3),a(4),b(4),
sum(1),sum(2),sum(3),sum(4),cout);
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-- GLOBAL Component Instantiation for Clock -- For FLEX devices, global should be replaced with aglobal u1: global PORT MAP (clk, gclk); |
-- GLOBAL Component Instantiation for Reset -- For FLEX devices, global should be replaced with aglobal u2: global PORT MAP (rst, grst); |
-- CLOCK process to create registered output clocked: PROCESS(gclk,grst) |
BEGIN
IF grst = '0' THEN
regsum <= "0000";
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ELSIF gclk'EVENT AND gclk = '1' THEN
regsum <= sum;
END IF;
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END PROCESS clocked; END MAX7000; |
Before you can analyze the 4-bit adder design, you must first analyze the fa4 description in Figure 1 with the Synopsys VHDL Compiler software. You can ignore the warning that is issued for any unknown function, including the fa4 function in this example. If you wish, you can avoid receiving such warning messages by creating a hollow-body description of the function.
A hollow-body VHDL description combines an Entity Declaration with an empty or null Architecture Body. An empty Architecture Body contains the ARCHITECTURE IS clause, followed by the BEGIN and END keywords and a semicolon (;). It does not include any information about the design's function or operation. Figure 2 shows the hollow-body description for the fa4 function.
| Figure 2. Hollow-Body Description of a 4-Bit Full Adder (7483) |
LIBRARY ieee; USE ieee.std_logic_1164.ALL; |
-- fa4 maps to 7483. The interface names do not have to match. ENTITY fa4 IS |
PORT (c0,a1,b1,a2,b2,a3,b3,a4,b4 : IN STD_LOGIC;
s1,s2,s3,s4,c4 : OUT STD_LOGIC);
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END fa4; ARCHITECTURE map7483 OF fa4 IS |
BEGIN -- This architecture body is left blank, and will map to the -- 7483 macrofunction in MAX+PLUS II. END; |
When you analyze the hollow-body design description with the Synopsys VHDL Compiler software, it produces a hollow-body component that contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.
You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the MAX+PLUS II software. After the VHDL Compiler software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.
Figure 3. Synthesized Design Generated by the Design Compiler
However, before you compile the EDIF netlist file with the MAX+PLUS II software, you must create the adder.lmf file, shown in Figure 3, to map the fa4 function to the equivalent MAX+PLUS II function (7483). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in MAX+PLUS II Help.
| Figure 3. Library Mapping File Excerpt for fa4 |
BEGIN FUNCTION 7483 (c0, a1, b1, a2, b2, a3, b3, a4, b4,) RETURNS (s1, s2, s3, s4, c4) |
FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
"b3","a4", "b4")
RETURNS ("s1", "s2", "s3", "s4", "c4")
END
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When you compile the design with the MAX+PLUS II software, you can disregard the warning "EDIF cell <name> already has LMF mapping so CONTENTS construct has been ignored". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the MAX+PLUS II Compiler.
You can instantiate a_8fadd, a_8mcomp, a_8count, and a_81mux functions, in VHDL designs. Altera provides behavioral descriptions of these functions that support pre-synthesis/pre-route simulation of your top-level design with the VHDL System Simulator (VSS).
When you instantiate one of these functions, you can either include a Component Declaration for the function, or use the Altera-provided shell script analyze_vss to create a design library called altera so that you can reference the functions through the VHDL Library and Use Clauses. The Library and Use Clauses direct the Design Compiler or FPGA Compiler to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library when it analyzes the VSS simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting up VSS Configuration Files for more information on using the analyze_vss shell script.
Figure 1 shows an example of an 8-bit counter that is instantiated using the a_8count function.
Figure 1. Sample VHDL File with Logic Function Instantiation
LIBRARY ieee; USE ieee.std_logic_1164.ALL; |
LIBRARY altera; USE altera.maxplus2.ALL; |
ENTITY counter IS PORT (clock,ena,load,dnup,set,clear : IN STD_LOGIC; i : IN STD_LOGIC_VECTOR (7 DOWNTO 0); q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); |
cout : OUT STD_LOGIC); END counter; |
ARCHITECTURE structure OF counter IS |
BEGIN u1 : a_8count |
PORT MAP (a=>i(0), b=>i(1), c=>i(2), d=>i(3), e=>i(4),
f=>i(5), g=>i(6), h=>i(7), ldn=>load, gn=>ena,
dnup=>dnup, setn=>set, clrn=>clear, clk=>clock,
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qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3), qe=>q(4),
qf=>q(5), qg=>q(6), qh=>q(7), cout=>cout);
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END structure; |
CONFIGURATION conf OF counter IS FOR structure END FOR; END conf; |
The Altera DesignWare Libraries for FLEX devices allow you to instantiate the DW03_updn_ctr function, which is the same as the Synopsys DW03 up/down counter. This function allows you to use the same VHDL code regardless of which
Figure 1 shows a VHDL file excerpt with DW03_updn_ctr instantiation.
| Figure 1. VHDL File Excerpt with Up/Down Counter Instantiation |
LIBRARY ieee,DW03; USE ieee.std_logic_1164.all; USE DW03.DW03_components.all; |
ENTITY updn_4 IS
PORT (D : IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
UP_DN, LD, CE, CLK, RST: IN STD_LOGIC;
TERCNT : OUT STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(4-1 DOWNTO 0));
END updn_4;
|
ARCHITECTURE structure OF updn_4 IS |
BEGIN
u0: DW03_updn_ctr
GENERIC MAP(width => 4)
PORT MAP (data => d, clk => clk, reset => rst, up_dn => up_dn,
load => ld, tercnt => tercnt, cen => ce, count => q);
END structure;
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| Go to Setting Up the DesignWare Interface in these MAX+PLUS II | |
Go to the following topics, which are available on the web, for additional information: | |
|
The genmem
at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.
To instantiate a RAM or ROM function in VHDL, follow these steps:
genmem <memory type> <memory size> -vhdl
For example: genmem asynrom 256x15 -vhdl
Figure 1 shows a VHDL design that instantiates asyn_rom_256x15.vhd, a 256 x 15 ROM function.
| Figure 1. VHDL Design File with ROM Instantiation (tstrom.vhd) |
LIBRARY ieee; USE ieee.std_logic_1164.all; |
ENTITY tstrom IS
PORT (
addr : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
memenab : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (14 DOWNTO 0));
END tstrom;
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ARCHITECTURE behavior OF tstrom IS
COMPONENT asyn_rom_256x15
-- pragma translate_off
GENERIC (LPM_FILE : string);
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-- pragma translate_on
PORT (Address : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
MemEnab : IN STD_LOGIC;
Q : OUT STD_LOGIC_VECTOR(14 DOWNTO 0)
);
END COMPONENT;
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BEGIN
u1: asyn_rom_256x15
-- pragma translate_off
GENERIC MAP (LPM_FILE => "u1.hex")
-- pragma translate_on
PORT MAP (Address => addr, MemEnab => memenab, Q =>q);
END behavior;
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LPM_FILE parameter. See Figure 1. The filename must be the same as the instance name; e.g., the u1 instance name must be unique throughout the whole project, and must contain only valid VHDL name characters. The initialization file must reside in the directory containing the project's design files.
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-- pragma translate_off -- pragma translate_on --pragma translate_off directive instructs the VHDL Compiler software to skip syntax checking until the --pragma translate_on directive is read.
string for the Generic Clause, you must also enter the following command before you read the design:
hdlin_translate_off_skip_text=true
read -f db flex10k[<speed grade>].db update_lib flex10k[<speed grade>] <RAM/ROM function name>.lib |
write_lib flex10k[<speed grade>] -o flex10k.db ![]()
Continue with the steps necessary to complete your VHDL design, as described in Creating VHDL Designs for Use with MAX+PLUS II Software.
| Go to FLEX 10K Device Family, which is available on the web, for additional information. |
clklock phase-locked loop megafunction, which can be used with some gencklk -h
at the UNIX prompt to display information on how to use this utility. The gencklk utility generates VHDL or Verilog HDL functional simulation models and a VHDL Component Declaration template file (.cmp).
The gencklk utility allows parameters for the clklock function to be passed from the VHDL or Verilog HDL file to EDIF netlist format. The gencklk utility embeds the parameter values in the clklock function name; therefore, the values do not need to be declared explicitly.
To instantiate the clklock megafunction in VHDL or Verilog HDL, go through the following steps:
clklock_x_y file, where x is the
Type gencklk <ClockBoost> <input frequency> -vhdl |
or:
Type gencklk <ClockBoost> <input frequency> -verilog |
Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information on the clklock megafunction.
clklock_x_y function. The gencklk utility automatically generates a VHDL Component Declaration template in the clklock_x_y.cmp file that you can incorporate into a VHDL design file.
Figures 1 and 2 show a clklock function with <ClockBoost> = 2 and <input frequency> = 40 MHz instantiated in VHDL and Verilog HDL design files, respectively.
| Figure 1. VHDL Design File with clklock Instantiation (count8.vhd) |
LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera; USE altera.maxplus2.all; -- Include Altera Component Declarations |
ENTITY count8 IS
PORT (a : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ldn : IN STD_LOGIC;
gn : IN STD_LOGIC;
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dnup : IN STD_LOGIC;
setn : IN STD_LOGIC;
clrn : IN STD_LOGIC;
clk : IN STD_LOGIC;
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co : OUT STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END count8;
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ARCHITECTURE structure OF count8 IS signal clk2x : STD_LOGIC; |
COMPONENT clklock_2_40
PORT (
INCLK : IN STD_LOGIC;
OUTCLK : OUT STD_LOGIC
);
END COMPONENT;
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BEGIN u1: clklock_2_40 PORT MAP (inclk=>clk, outclk=>clk2x); |
u2: a_8count
PORT MAP (a=>a(0), b=>a(1), c=>a(2), d=>a(3),
e=>a(4), f=>a(5), g=>a(6), h=>a(7),
clk=>clk2x,
ldn=>ldn,
gn=>gn,
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dnup=>dnup,
setn=>setn,
clrn=>clrn,
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qa=>q(0), qb=>q(1), qc=>q(2), qd=>q(3),
qe=>q(4), qf=>q(5), qg=>q(6), qh=>q(7),
cout=>co);
END structure;
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| Figure 2. Verilog HDL Design File with clklock Instantiation (count8.v) |
`timescale 1ns / 10ps module count8 (a, ldn, gn, dnup, setn, clrn, clk, co, q); output co; output[7:0] q; |
input[7:0] a; input ldn, gn,dnup, setn, clrn, clk; wire clk2x; |
clklock_2_40 u1 (.inclk(clk), .outclk(clk2x) ); A_8COUNT u2 (.A(a[0]), .B(a[1]), .C(a[2]), .D(a[3]), .E(a[4]), .F(a[5]), |
.G(a[6]), .H(a[7]), .LDN(ldn), .GN(gn), .DNUP(dnup),
.SETN(setn), .CLRN(clrn), .CLK(clk2x), .QA(q[0]), .QB(q[1]),
.QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]), .QG(q[6]),
.QH(q[7]), .COUT(co) );
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endmodule |
| Go to FLEX 10K Device Family, which is available on the web, for additional information. |
You can create Verilog HDL design files with the
Once you have created a Verilog HDL design, you can use the Design Compiler or FPGA Compiler to synthesize and optimize it, and then generate an EDIF netlist file that can be processed with the MAX+PLUS II software.
To create a Verilog HDL design that can be synthesized and optimized with the Design Compiler or FPGA Compiler, follow these steps:
a_8count, a_8mcomp, a_8fadd, and a_81mux functions. See MAX+PLUS II Architecture Control Logic Function Instantiation Example for Verilog HDL for an example.
clklock megafunction, which is supported for selected FLEX 10K devices. This function is generated with the gencklk utility. Go to Instantiating the clklock Megafunction in VHDL or Verilog HDL for instructions.
You can also instantiate any other Altera macrofunction or non-parameterized megafunction, i.e., functions not listed above, for which no simulation models or technology library support is available. These functions are treated as "black boxes" during processing with the Design Compiler or FPGA Compiler. See Primitive & Old-Style Macrofunction Instantiation Example for Verilog HDL for an example.
For information on MAX+PLUS II primitives, megafunctions, and macrofunctions, choose Primitives, Megafunctions/LPM, or Old-Style Macrofunctions from the MAX+PLUS II Help menu. When searching for information on the alt_mf library functions, drop the initial "a_" from the function name.
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| If you instantiate a "black box" logic function, you must create a Library Mapping File (.lmf) to map the function to an equivalent MAX+PLUS II function before you compile the project with the MAX+PLUS II software. See Primitive & Old-Style Macrofunction Instantiation Example for VHDL for an example. |
Installing the Altera-provided MAX+PLUS II/Synopsys Logic interface on your computer automatically creates the following VHDL sample files:
| Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II | |
You can instantiate the
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Go to the following topics for information and examples of how to instantiate functions that are not considered to be hollow bodies, including functions in the alt_mf library, RAM and ROM, and the
|
Unlike other logic functions, MAX+PLUS II primitives do not need to be defined with hollow-body functions unless you wish to simulate the design with the VHDL System Simulator (VSS) software. Any references to these primitives are resolved by the Synopsys compilers. All buffer primitives except the ATRIBUF and TRIBUF primitives also have a "don't touch" attribute already assigned to them, which prevents the Synopsys compilers from optimizing them. The Synopsys compilers also automatically treat mega- and macrofunctions that do not have corresponding synthesis library models as "black boxes."
Figure 1 shows a 4-bit full adder with registered output that also instantiates an AGLOBAL or GLOBAL primitive. This figure also illustrates the use of global Clock and global Reset pins in the MAX 7000 architecture. The design uses an old-style 7483 macrofunction, which is represented as a hollow body named fa4.
| Figure 1. 4-Bit Adder Design with Registered Output (adder.v) | |
module adder (a, b, clk, rst, cout, regsum); output cout; output[4:1] regsum; input[4:1] a, b; input clk, rst; wire[4:1] sum; reg[4:1] regsum_int; wire grst, gclk; wire ci; assign ci = 0; | |
// module instantiation
fa4 u0 ( .c0(ci), .a1(a[1]), .b1(b[1]), .a2(a[2]),
.b2(b[2]), .a3(a[3]), .b3(b[3]), .a4(a[4]),
.b4(b[4]), .s1(sum[1]), .s2(sum[2]),
.s3(sum[3]), .s4(sum[4]), .c4(cout));
// For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced
// with AGLOBAL, IN1, and Y, respectively
GLOBAL u1 ( .A_IN(clk), .A_OUT(gclk));
GLOBAL u2 ( .A_IN(rst), .A_OUT(grst));
| |
always @(posedge gclk or negedge grst)
if ( !grst )
regsum_int = 4'b0;
else regsum_int = sum;
assign regsum = regsum_int;
endmodule
| |
// module declaration for fa4 module module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4); | |
output s1, s2, s3, s4, c4; input c0, a1, b1, a2, b2, a3, b3, a4, b4; endmodule | |
// module declaration for GLOBAL primitive // For FLEX devices, GLOBAL, A_IN, and A_OUT should be replaced // with AGLOBAL, IN1, and Y, respectively module GLOBAL (A_OUT, A_IN); | |
input A_IN; output A_OUT; endmodule | |
You can analyze the 4-bit adder design with the Synopsys HDL Compiler for Verilog software. The hollow-body description of the fa4 function is required. It contains port declarations and does not include any information about the design's function or operation. However, the hollow-body description can be in the design file, as shown in Figure 1, or in a separate file, as shown in Figure 2.
| Figure 2. Hollow-Body Description of a 4-Bit Full Adder (7483) |
module fa4 ( c0, a1, b1, a2, b2, a3, b3, a4, b4, s1, s2, s3, s4, c4); output s1, s2, s3, s4, c4; input c0, a1, b1, a2, b2, a3, b3, a4, b4; endmodule |
If the hollow-body description is in a separate file, you must analyze it before analyzing the higher-level function with the HDL Compiler for Verilog to produce a hollow-body component. This component contains a single level of hierarchy with input and output pins, but does not contain any underlying logic.
You can save the synthesized design as an EDIF netlist file (.edf) and compile it with the MAX+PLUS II software. After the HDL Compiler for Verilog software has successfully processed the design, it generates the schematic shown in Figure 3, which you can view with the Design Analyzer software.
Figure 3. Synthesized Design Generated by the Design Compiler
However, before you compile the EDIF netlist file with the MAX+PLUS II software, you must create the adder.lmf file, shown in Figure 3, to map the fa4 function to the equivalent MAX+PLUS II function (7483). You must then specify the LMF as LMF #2 in the expanded EDIF Netlist Reader Settings dialog box (Interfaces menu) (LMF #1 is altsyn.lmf). For more information about creating LMFs, refer to "Library Mapping Files (.lmf)" and "Library Mapping File Format" in MAX+PLUS II Help.
| Figure 3. Library Mapping File Excerpt for fa4 |
BEGIN FUNCTION 7483 (c0, a1, b1, a2, b2, a3, b3, a4, b4,) RETURNS (s1, s2, s3, s4, c4) |
FUNCTION "fa4" ("c0", "a1", "b1", "a2", "b2", "a3",
"b3","a4", "b4")
RETURNS ("s1", "s2", "s3", "s4", "c4")
END
|
When you compile the design with the MAX+PLUS II software, you can disregard the warning "EDIF cell <name> already has LMF mapping so CONTENTS construct has been ignored". To verify the global Clock and global Reset usage, as well as the number of logic cells used, see the adder.rpt Report File generated by the MAX+PLUS II Compiler.
You can instantiate a_8fadd, a_8mcomp, a_8count, and a_81mux functions, in Verilog HDL designs. Altera provides behavioral Verilog HDL descriptions of these functions.
Figure 1 shows an example of an 8-bit counter that is instantiated using the a_8count function. Because Verilog HDL is case-sensitive, be sure to use uppercase letters for all of the macrofunction's module names and port names.
Figure 1. Sample Verilog HDL File with Logic Function Instantiation (counter.v)
module counter (clock, ena, load, dnup, set, clear, i, q, cout);
output cout;
output[7:0] q;
input[7:0] i;
input clock, ena, load, dnup, set, clear;
A_8COUNT u1 (.A(i[0]), .B(i[1]), .C(i[2]), .D(i[3]),
.E(i[4]), .F(i[5]), .G(i[6]), .H(i[7]),
.LDN(load), .GN(ena), .DNUP(dnup), .SETN(set),
.CLRN(clear), .CLK(clock), .QA(q[0]), .QB(q[1]),
.QC(q[2]), .QD(q[3]), .QE(q[4]), .QF(q[5]),
.QG(q[6]), .QH(q[7]), .COUT(cout) );
endmodule
The sample file shown in Figure 1 can be synthesized with the Design Compiler or FPGA Compiler. You can also simulate it with the Cadence Verilog-XL Simulator by typing the following command at the dc_shell prompt:
verilog counter.v /usr/maxplus2/synopsys/library/alt_mf/src/mf.v ![]()
The genmem
at the UNIX prompt to display information on how to use this utility, as well as a list of the functions you can generate.
To instantiate a RAM or ROM function in Verilog HDL, follow these steps:
genmem <memory type> <memory size> -verilog
For example: genmem asynrom 256x15 -verilog
Figure 1 shows a Verilog HDL design that instantiates asyn_rom_256x15.v, a 256 x 15 ROM function.
| Figure 1. Verilog HDL File with ROM Instantiation (tstrom.v) |
module tstrom (addr, enab, q); parameter LPM_FILE = "u1.hex"; input [7:0] addr; input enab; output [14:0] q; |
asyn_rom_256x15
// synopsys translate_off
#(LPM_FILE)
|
// synopsys translate_on
u1 (.Address(addr), .Q(q), .MemEnab(enab));
endmodule
|
LPM_FILE parameter. See Figure 1. The filename must be the same as the instance name; e.g., the u1 instance name must be unique throughout the whole project. The initialization file must reside in the directory containing the project's design files.
| |
|
// synopsys translate_off // synopsys translate_on read -f db flex10k[<speed grade>].db update_lib flex10k[<speed grade>] <RAM/ROM function name>.lib |
write_lib flex10k[<speed grade>] -o flex10k.db ![]()
| Go to FLEX 10K Device Family, which is available on the web, for additional information. |
The
| You can also run Synopsys tools from within the MAX+PLUS II software to automatically generate and import an EDIF file. Refer to Running Synopsys Compilers from MAX+PLUS II Software for more information. In addition, if your MAX+PLUS II development system includes VHDL or Verilog HDL synthesis support, the MAX+PLUS II Compiler can directly synthesize VHDL or Verilog HDL logic. For more information, go to MAX+PLUS II VHDL or Verilog HDL Help. |
The following steps explain how to synthesize and optimize a VHDL or Verilog HDL design for use with MAX+PLUS II software:
dc_shell fpga_shell design_analyzer string for the Generic Clause, you must also enter the following command at the dc_shell prompt before you read the design:
hdlin_translate_off_skip_text=true
read -f db flex10k[<speed grade>].db update_lib flex10k[<speed grade>] <RAM/ROM function name>.lib |
write_lib flex10k[<speed grade>] -o flex10k.db ![]()
See Instantiating RAM & ROM Functions in VHDL or Instantiating RAM & ROM functions in Verilog HDL for additional information.
dc_shell prompt before compiling the design:
edifout_write_properties_list = "lut function" ![]()
Go to Using FPGA Compiler N-Input LUT Optimization for FLEX 6000, FLEX 8000, or FLEX 10K Devices for more information.
dc_shell prompt before compiling the design:
set_structure false set_flatten -effort low See MAX 7000 & MAX 9000 Synthesis Example for more information.
For additional information on how the Design Compiler and FPGA Compiler synthesize and optimize a design, see the following topics:
report_timing report_reference > <filename> Installing the Altera-provided MAX+PLUS II/Synopsys interface on your computer automatically creates the following sample VHDL and Verilog HDL files:
| Go to the following MAX+PLUS II | |
|
The
Figure 1 shows two timing models: the standard Altera MAX 7000 timing model and a Synopsys timing model that approximates the MAX 7000 model. The Synopsys model is built on the following three conditions and assumptions:
OR gates. Because the product-term delay equals the OR-gate delay, the Synopsys compilers treat them equally, producing a sum-of-products structure. On top of this structure, inverters are used where necessary.
Figure 1. Standard MAX 7000 Timing Model vs. Synopsys Approximation of Timing Model
If you wish to direct the Synopsys Design Compiler or FPGA Compiler software to produce sum-of-products logic that approximates the MAX 7000 or MAX 9000 timing model, you can type the following dc_shell prompt commands at the command line before compiling the design:
set_structure false ![]()
set_flatten -effort low ![]()
When set_structure is set to false, structuring is turned off, and the Synopsys Design Compiler and FPGA Compiler software cannot factor and share logic between functions. If you do not enter these commands, the Synopsys compilers may add logic, which can create additional area and timing delays.
Figure 2 shows a combinatorial design that is predictable when structuring is turned off, but is unpredictable when structuring is turned on.
Figure 2. Nonstructured vs. Structured Combinatorial Design
When you use low as the argument to the set_flatten -effort command, the Synopsys compilers use the shortest compilation time to create the sum-of-products implementation of your design. If you use the medium or high argument, the Synopsys compilers create optimally flattened designs, but usually require greater compilation time and offer little improvement in timing and area results.
You can type report_timing
after compilation to view Synopsys-generated timing information.
If you wish to calculate the area of your design, you can obtain an approximate logic cell count in several ways. Altera recommends that you add the number of registers and combinatorial outputs in a design. Depending on your design, this number may be slightly lower than the final number reported by the MAX+PLUS II software.
To create a file detailing primitive usage in the design, type report_reference> <filename>
after Synopsys compilation.
| To obtain accurate timing information about your design, you must use the MAX+PLUS II Timing Analyzer to analyze your design. For accurate area information, consult the Report File (.rpt) generated by the MAX+PLUS II software. |
| Refer to the following sources for related information: | |||
|
Figure 1 shows a sample VHDL design, design_one.vhd, which illustrates component inference with the DesignWare interface for
| Figure 1. VHDL Design File (design_one.vhd) |
This design illustrates the sum of A + B.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.ALL; |
ENTITY design_one IS
PORT (a,b : IN STD_LOGIC_VECTOR (7 DOWNTO 0);
f : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
END design_one;
|
ARCHITECTURE add_design OF design_one IS |
BEGIN f <= a + b; END add_design; |
When the VHDL Compiler or the HDL Compiler for Verilog software analyzes and elaborates the design, it replaces the "+" operator with its synthetic operator equivalent.
Figure 2 shows the design as it appears in the Design Analyzer software after it has been analyzed and elaborated by the VHDL Compiler software.
Figure 2. design_one.vhd after Analysis & Elaboration
When you synthesize a design, the Design Compiler or FPGA Compiler software uses the synthetic library to match the synthetic operator to the FLEX-optimized logical implementation in the technology library. The Synopsys Design Compiler or FPGA Compiler software then instantiates and interconnects the correct number of flex_add and flex_carry functions to produce the 8-bit adder shown in Figure 1. When you save a compiled design as a VHDL, Verilog HDL or EDIF file, the file preserves the number of flex_add and flex_carry functions, as well as their interconnections. Consequently, area and performance predictions that you make in the Synopsys design environment closely match the final
Table 2 lists functions included in the DesignWare FLEX 6000, FLEX 8000, and FLEX 10K synthetic libraries.
| Table 2. FLEX 6000, FLEX 8000, and FLEX 10K Synthetic Library Functions | |
| Name | Function |
|---|---|
flex_add |
Sum of A, B, and Carry-In |
flex_carry
| Carry of A, B, and Carry-In |
flex_sub |
Difference of A, B, and Borrow-In |
flex_borrow
| Borrow of A, B, and Borrow-In |
flex_gt, flex_sgt
| Greater than (flex_gt is unsigned; flex_sgt is signed)
|
flex_carry_gt
| Greater than Carry |
flex_lt, flex_slt
| Less than (flex_lt is unsigned; flex_slt is signed)
|
flex_carry_lt
| Less than Carry |
flex_gteq, flex_sgteq
| Greater than or equal to (flex_gteq is unsigned; flex_sgteq is signed)
|
flex_carry_gteq
| Greater than or equal to Carry |
flex_inc |
Incrementer (Count = Count + 1) |
flex_carry_inc
| Incrementer Carry (Count = Count + 1) |
flex_dec |
Decrementer (Count = Count - 1) |
flex_carry_dec
| Decrementer Carry (Count = Count - 1) |
flex_lteq, flex_slteq
| Less than or equal to (flex_lteq is unsigned; flex_slteq is signed)
|
flex_carry_lteq
| Less than or equal to Carry |
flex_count
| Counter |
aflex_carry_count
| Counter Carry |
flex_add_sub
| Adder/Subtractor |
flex_inc_dec
| Incrementer/Decrementer |
flex_umult, flex_smult
| Multiplier (flex_umult is unsigned; flex_smult is signed)
|
Figure 3 shows design_one.vhd after it has been synthesized with the Design Compiler.
Figure 3. design_one.vhd Synthesized & Resolved for FLEX 6000, FLEX 8000 & FLEX 10K Architecture
After you save the design as an EDIF Input File (.edf) and process it with the MAX+PLUS II Compiler, the Compiler replaces instances of flex_add and flex_carry with FLEX-optimized versions, as shown in Figure 4. The MAX+PLUS II Compiler maps these functions into a single logic element (LE). The result is a high-speed 8-bit adder that fits into 8 LEs.
Figure 4. One Slice of the design_one 8-bit Adder Design with Optimized FLEX 8000 Functions
| Refer to the following sources for related information on DesignWare and the Synopsys VHDL Compiler: | |
|
Go to FLEX Devices, which is available on the web, for additional information: |
The Synopsys FPGA Compiler software supports an N-input look-up table (LUT) function that improves the quality of the results and the predictability of delay and resource estimates. All
Figure 1 shows a sample command sequence that FPGA Compiler might require for N-input LUT optimization. To use N-input LUT optimization, include the edifout_write_properties_list = "lut_function" command.
| Figure 1. Sample Command Sequence for N-Input LUT Optimization |
read -f vhdl <design name>.vhd current_design = <design name> set_max_area 0 uniquify ungroup -all -flatten compile -ungroup_all report_area > <design name>.rpa report_fpga > <design name>.rpf report_cell > <design name>.rpc edifout_write_properties_list = "lut_function" write -f edif -hierarchy -o <design name>.edf |
Use the area report to determine the circuit area.
If you wish to maintain area report estimates as closely as possible during
| For more information on how to use the FPGA Compiler software optimize your design for FLEX 8000 devices, refer to Chapter 5: Optimization for the Altera FLEX 8000 Architecture in the Synopsys FPGA Compiler User Guide. | |
Go to FLEX Devices, which is available on the web, for additional information: |
The
In designs targeted for the Synopsys Design Compiler and FPGA Compiler software,
you can assign a limited subset of these resource assignments
by setting attributes in the VHDL or Verilog HDL design files with the set_attribute command. These attributes are incorporated
into the EDIF netlist file(s). The MAX+PLUS II software automatically converts
assignment information from the EDIF Input File (.edf) into the ACF format.
For information on making MAX+PLUS II-compatible resource assignments with the set_attribute command, go to the following topics:
You can also modify the ACF for a design to contain timing requirements and other assignments, as described in the following topics:
Refer to the following sources for related information:
|
You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device.
You can assign a signal to a particular
pin to ensure that the signal is always associated with that pin,
regardless of future changes to the project. If you wish to set
and maintain the performance of your project, assigning logic
to a specific logic cell within a chip can minimize timing delays.
In a project that is partitioned among multiple devices, you can
assign logic functions that must be kept together in the same
device to a chip. Chip assignments allow you to split a project
so that only a minimum number of signals travel between devices,
and to ensure that no unnecessary device-to-device delays exist
on critical timing paths. You can assign a chip to a device in
To make pin, logic cell, and chip assignments, use the set_attribute command at a dc_shell prompt. Before using the set_attribute command, add the following line to your .synopsys_dc.setup file:
edifout_write_properties_list = {LOGIC_OPTION, CLIQUE, CHIP_PIN_LC}
Table 1 shows the syntax to use for chip, pin, and logic cell assignments:
| Table 1. Commands for Chip, Pin, & Logic Cell Assignments | |
| Chip | set_attribute find (<design object>, (<instance name>)) "CHIP_PIN_LC" -type string "<chip name>" |
| Pin | set_attribute find (<design object>, (<instance name>)) "CHIP_PIN_LC" -type string "<chip name>@<pin number>" |
| Logic cell number | set_attribute find (<design object>, (<instance name>)) "CHIP_PIN_LC" -type string "<chip name>@LC<logic cell number>" |
| I/O cell number | set_attribute find (<design object>, (<instance name>)) "CHIP_PIN_LC" -type string "<chip name>@IOC<I/O cell number>" |
| Embedded cell number | set_attribute find (<design object>, (<instance name>)) "CHIP_PIN_LC" -type string "<chip name>@EC<embedded cell number>" |
Note:
Examples:
set_attribute find (cell, (U1))
"CHIP_PIN_LC" -type string "chip1" ![]()
set_attribute find
(cell, (U1)) "CHIP_PIN_LC" -type string "chip1@K2" ![]()
set_attribute find
(cell, (U1)) "CHIP_PIN_LC" -type string "chip1@LC44" ![]()
| Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software. | |
You can define a group of logic functions
as a single, named unit, called a clique. The
To make pin, logic cell, and chip assignments, use the set_attribute command at a dc_shell prompt. Before using the set_attribute command, add the following line to your .synopsys_dc.setup file:
edifout_write_properties_list = {LOGIC_OPTION, CLIQUE, CHIP_PIN_LC}
| |
To assign a clique, type the following command at a dc_shell prompt: |
set_attribute find(<design object>,(<instance name>))"CLIQUE" -type string "<clique name>" | |
For example:set_attribute find (cell, (U1)) "CLIQUE" -type string "fast1" |
Go to the following topics in MAX+PLUS II Help for related information: | |
|
Logic options and logic synthesis style
assignments allow you to guide logic synthesis with logic optimization
features that are specific to
To make pin, logic cell, and chip assignments, use the set_attribute command at a dc_shell prompt. Before using the set_attribute command, add the following line to your .synopsys_dc.setup file:
edifout_write_properties_list = {LOGIC_OPTION, CLIQUE, CHIP_PIN_LC} ![]()
| To assign a logic option or a logic synthesis style, type the following command at a dc_shell prompt: | |
set_attribute find(<design object>, (<instance name>)) "LOGIC_OPTION" <logic option>=<value>" | |
| For example: | |
set_attribute find (cell, (U1)) "LOGIC_OPTION" -type string | |
| To specify multiple logic options, use commas as separators. | |
| For example: | |
set_attribute find (cell, (U1))"LOGIC_OPTION" -type string "STYLE=FAST, |
| Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments. |
Altera provides the setacf utility to help you modify a project's Assignment & Configuration File (.acf) from the command line, without opening the file with a text editor. Type setacf -h
at a UNIX or DOS prompt to get help on this utility.
Altera provides the syn2acf
utility, which is an interface program that converts Synopsys
timing constraints from non-hierarchical designs into the
The syn2acf utility requires the following input files:
To use the syn2acf utility, follow these steps:
Set the timing constraints by using one of the following methods:
| Start the Synopsys Design Analyzer and specify timing constraints by choosing appropriate menu commands. |
or:
| Create the <design name>.cmd file for use with a dc_shell script. See Figure 1. |
The syn2acf
utility does not support set_arrival
timing constraints for internal nodes. |
Figure 1. Sample Command File (.cmd) for Setting Timing Constraints
create_clock -period 50 -waveform {0 25} CLK
set_clock_skew -delay 2 CLK
set_input_delay 10 IN2
set_input_delay 5 -clock CLK IN1
set_output_delay 20 OUT2
set_output_delay 5 -clock CLK OUT1
set_max_delay 25 -to OUT1
set_max_delay 35 -to OUT2
set_multicycle_path 2 -to n20_reg
|
Compile the design, then type the
following command from the UNIX prompt to start the syn2acf
utility:
/usr/maxplus2/synopsys/bin/syn2acf
<design name> |
or:
| Run a dc script inside the dc_shell script that reads the VHDL design, compiles it, and runs the syn2acf utility. Figure 2 shows a sample dc script. |
The syn2acf
utility uses the ALT_HOME
environment variable, if it has been specified, to determine the
MAX+PLUS II system directory; otherwise, it uses the
/usr/maxplus2
directory. To specify a different MAX+PLUS II system directory
with the ALT_HOME
environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:
setenv
ALT_HOME <MAX+PLUS II
system directory> |
Figure 2. Sample Script for Running the syn2acf Utility
/* dc_script example to interface with syn2acf */ |
||
dc_shell <<! |
||
read -f vhdl <design name>.vhd |
||
include <design name>.cmd |
/*set timing constraints*/ |
|
compile
|
||
current_design=<design name> |
||
include /usr/maxplus2/synopsys/bin/syn2acf.cmd |
/*generate required files*/ |
|
sh /usr/maxplus2/synopsys/bin/syn2acf <design name> |
/*invoke syn2acf utility*/ |
|
quit |
||
! |
||
The
syn2acf
utility cannot support maximum Clock frequency (fMAX)
correctly if more than one Clock skew is specified in the dc_shell
command script. This problem occurs because the Synopsys write_script
command drops the Clock skew information for the registers. The
syn2acf
utility will use the last Clock skew number to calculate fMAX. |
The sample dc
script includes the
Figure 3. Altera-Provided syn2acf.cmd File
ungroup -flatten -all write -f edif write_script > altsyn.dc write_constraints -format sdf -cover_design write_timing -format sdf |
All timing assignments generated by
the syn2acf
utility are written to the Timing Requirement Assignments Section
of the project's ACF, with the assignment source identifier
{synopsys}
at the end of each line. Figure 4
shows a sample ACF excerpt that contains Synopsys timing constraints
generated by the syn2acf
utility.
Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints
TIMING_POINT
BEGIN
"|OUT2" : TCO = 15.00ns {synopsys};
"|IN1" : TPD = 10.00ns {synopsys};
"|IN2" : TPD = 5.00ns {synopsys};
"|OUT1" : TCO = 20.00ns {synopsys};
"|IN1" : TSU = 20.00ns {synopsys};
"|IN2" : TSU = 117.00ns {synopsys};
"|CLK" : FREQUENCY = 50.00ns {synopsys};
"|n10_reg" : FREQUENCY = 100.00ns {synopsys};
END;
|
Altera provides sample files for these utilities in the /usr/maxplus2/synopsys/bin directory.
Altera provides the gen_hacf and gen_iacf
utilities, which convert Synopsys timing constraints into the
To use the gen_iacf and gen_hacf utilities, follow these steps:
| You can create a dc_shell script that performs most of these steps. Refer to Figure 2 for a sample dc_shell script. |
The gen_iacf and gen_hacf
utilities use the ALT_HOME
environment variable, if it has been specified, to determine the
MAX+PLUS II system directory; otherwise, it uses the
/usr/maxplus2
directory. To specify a different MAX+PLUS II system directory
with the ALT_HOME
environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:
setenv
ALT_HOME <MAX+PLUS II
system directory> |
write -f edif -hierarchy <top-level design name> -o <top-level design name>.hier.edf ![]()
The gen_iacf and gen_hacf
utilities do not support set_arrival
timing constraints for internal nodes. |
Figure 1. Sample gen_iacf.cmd File
ungroup -flatten -all |
write -f edif |
write_script > <design_name> + "_setup.dc" |
write_constraints -format sdf -cover_design |
write_timing -format sdf |
This sample command file assumes that the design_name variable has been set before the command file is included. |
gen_iacf <design name> ![]()
gen_hacf <top-level design name>[<sub-design file list>] ![]()
Figure 2 shows a sample dc_shell script, which includes all of the steps for using the gen_iacf and gen_hacf utilities.
Figure 2. Sample Script for Running the gen_iacf and gen_hacf Utilities
/* Sample dc_shell script for converting hierarchical Synopsys timing constraints to the ACF format The example design TOP has 3 lower-level subdesigns - LOWER1, LOWER2, LOWER3. Only LOWER1, LOWER2 and TOP designs have constraints. */ link_library = flex10k-3.db target_library = flex10k-3.db synthetic_library = flex10k-3.sldb read -f vhdl LOWER1.vhd read -f vhdl LOWER2.vhd read -f vhdl LOWER3.vhd read -f vhdl TOP.vhd elaborate LOWER1 current_design=LOWER1 /* Include user-defined timing constraints for LOWER1 */ include timing1.cmd compile design_name=LOWER1 /* generate input files for gen_iacf */ include /usr/maxplus2/synopsys/bin/gen_iacf.cmd /* generate an intermediate ACF (.iacf) file for LOWER1 design */ sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER1 elaborate LOWER2 current_design=LOWER2 /* Include user-defined timing constraints for LOWER2 */ include timing2.cmd compile design_name=LOWER2 /* generate input files for gen_iacf */ include /usr/maxplus2/synopsys/bin/gen_iacf.cmd /* generate an intermediate ACF (.iacf) file for LOWER2 design */ sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER2 elaborate TOP current_design=TOP /* Include user-defined timing constraints for TOP */ include timing3.cmd compile /* generate a hierarchical EDIF netlist file for the top-level design before it is flattened by the gen_iacf.cmd utility */ write -f edif -hierarchy TOP -o TOP.hier.edf design_name=TOP /* generate input files for gen_iacf */ include /usr/maxplus2/synopsys/bin/gen_iacf.cmd /* generate an intermediate ACF (.iacf) file for design TOP */ sh /usr/maxplus2/synopsys/bin/gen_iacf TOP /* Rename the hierarchical EDIF netlist file generated earlier to <top level design>.edf, which is required by gen_hacf utility and MAX+PLUS II */ sh mv TOP.hier.edf TOP.edf /* Merge all .iacf files to generate the final top-level ACF File subdesign.list in the following command lists the names of subdesigns that have timing constraints, one per line. In this example it has 2 lines, one each for LOWER1 and LOWER2. Top-level design name should not be specified in this file. */ sh /usr/maxplus2/synopsys/bin/gen_hacf TOP subdesign.list quit
The
gen_iacf
utility cannot support maximum Clock frequency (fMAX)
correctly if more than one Clock skew is specified in the dc_shell
command script. This problem occurs because the Synopsys write_script
command drops the Clock skew information for the registers. The
gen_iacf
utility will use the last Clock skew number to calculate fMAX. |
All timing assignments generated by
the gen_iacf
utility are written to the Timing Requirement Assignments Section
of the project's ACF, with the assignment source identifier
{synopsys}
at the end of each line. Figure 4
shows a sample ACF excerpt that contains Synopsys timing constraints
generated by the gen_iacf
utility.
Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints
TIMING_POINT
BEGIN
"|OUT2" : TCO = 15.00ns {synopsys};
"|IN1" : TPD = 10.00ns {synopsys};
"|IN2" : TPD = 5.00ns {synopsys};
"|OUT1" : TCO = 20.00ns {synopsys};
"|IN1" : TSU = 20.00ns {synopsys};
"|IN2" : TSU = 117.00ns {synopsys};
"|CLK" : FREQUENCY = 50.00ns {synopsys};
"|n10_reg" : FREQUENCY = 100.00ns {synopsys};
END;
|
The MAX+PLUS II Compiler flattens the design internally before compiling it, which may convert some of the ports on the sub-designs into internal or buried nodes. In addition, the gen_iacf and gen_hacf utilities will correctly pass tCO and tPD assignments made at lower levels of hierarchy to the ACF, but the MAX+PLUS II Compiler will ignore them and generate one or more warning messages (e.g., Warning: Ignored timing assignment for tsu|tpd|tco on buried node |TIME_STATE_MACHING:U1|tb1_3:U115|:30). In addition, hierarchical timing constraints may result in duplicate assignments in the ACF, and the MAX+PLUS II Compiler could generate an additional warning (e.g., Warning: Ignored redefinition of resources assignment (logic option assignment) for node 'CLK' Processing . . . ).
|
After you have synthesized and optimized a VHDL or Verilog HDL design with the Design Compiler or FPGA Compiler software, you can perform a pre-routing or functional simulation with the Synopsys VHDL System Simulator (VSS) software.
To perform a pre-routing/functional simulation, follow these steps:
| VSS requires each architecture/entity pair in a VHDL Design File to have a configuration. The Configuration Declaration is necessary for simulation, but not for synthesis. |
| Refer to the following sources for related information: | |
|
Altera provides the alt_vtl.db post-synthesis library for technology mapping or resynthesis. You can use this library with the
To retarget and resynthsize a design, follow these steps:
search_path = {./usr/maxplus2/synopsys/library/alt_post/syn/lib
<target library path>}; 
target_library = {<target library path>}; 
symbol_library = {<target library symbol file>}; 
link_library = {alt_vtl.db}; 
read -f edif <design name>.edo 
read_timing -load_delay net <design name>.sdo compile 
report_timing 
write -f edif -hierarchy -o <design name>.edf 
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