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MAX+PLUS II Architecture Control Logic Function Instantiation Example for VHDLYou can instantiate When you instantiate one of these functions, you can either include a Component Declaration for the function, or use the Altera-provided shell script analyze_vss to create a design library called altera so that you can reference the functions through the VHDL Library and Use Clauses. The Library and Use Clauses direct the Design Compiler or FPGA Compiler to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library when it analyzes the VSS simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting up VSS Configuration Files for more information on using the analyze_vss shell script. Figure 1 shows an example of an 8-bit counter that is instantiated using the Figure 1. Sample VHDL File with Logic Function Instantiation
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||||||||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||||||||||