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Updating DesignWare Libraries

Although Altera provides DesignWare libraries that are pre-compiled for the current version of Synopsys tools, you may wish to recompile the libraries.

Altera provides compilable source files and scripts that allow you to automate the compilation process. These source files allow you to use DesignWare software with any version of the Design Compiler or FPGA Compiler software.They also allow you to install components whose source is written in VHDL, even if you are licensed only for the Verilog HDL Compiler software.

Source files for the Design Compiler software are automatically installed in the following directories:

  • /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]
  • /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]
  • /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>

Source files for the FPGA Compiler are automatically installed in the following directories:

  • /usr/maxplus2/synopsys/library/alt_syn/flex10k/src/dw_flex10k[<speed grade>]_fpga
  • /usr/maxplus2/synopsys/library/alt_syn/flex8000/src/dw_flex8000[<speed grade>]_fpga
  • /usr/maxplus2/synopsys/library/alt_syn/flex6000/src/dw_flex6000<speed grade>_fpga

You can compile the VHDL source file for use with the appropriate library. Refer to Table 1 to determine which commands you should type at the UNIX prompt to compile the library.

Table 1. Commands for Compiling the Library
Device Family Synopsys Compiler
Commands for Compiling the Library Note (1)
FLEX®6000 Design Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/
src/dw_flex6000
<speed grade> Enter
dw_flex6000.script Enter
FPGA Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex6000/
src/dw_flex6000
<speed grade>_fpga Enter
dw_flex6000.script Enter
FLEX 8000 Design Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/
src/dw_flex8000[
<speed grade>] Enter
dw_flex8000.script Enter
FPGA Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex8000/
src/dw_flex8000[
<speed grade>]_fpga Enter
dw_flex8000.script Enter
FLEX  10K Design Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/
src/dw_flex10k[
<speed grade>] Enter
dw_flex10k.script Enter
FPGA Compiler cd /usr/maxplus2/synopsys/library/alt_syn/flex10k/
src/dw_flex10k[
<speed grade>]_fpga Enter
dw_flex10k.script Enter

Notes:

  1. For FLEX 6000 devices, you must specify either -2 or -3 for the <speed grade> variable. For FLEX 8000 and FLEX 10K devices, you must specify -2, -3, -4, -5, or -6; or -1, -2, -3, -4, or -5; respectively, for the <speed grade> variable.


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Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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