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Converting Synopsys Hierarchical Timing Constraints into MAX+PLUS II-Compatible Format with the gen_iacf and gen_hacf Utilities

Altera provides the gen_hacf and gen_iacf utilities, which convert Synopsys timing constraints into the MAX+PLUS® II Assignment & Configuration File (.acf) format. For information on converting timing constraints from non-hierarchical designs, refer to Converting Synopsys Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility. The gen_iacf utility generates intermediate, individual ACFs with the extension .iacf for each subdesign. The gen_hacf utility merges the individual .iacf files into a single ACF for the whole design.

To use the gen_iacf and gen_hacf utilities, follow these steps:

Note: You can create a dc_shell script that performs most of these steps. Refer to Figure 2 for a sample dc_shell script.

  1. Make sure that you have specified the correct path of your local Perl executable, as specified in step 5 of Setting Up the MAX+PLUS II/Synopsys Working Environment.

    Note: The gen_iacf and gen_hacf utilities use the ALT_HOME environment variable, if it has been specified, to determine the MAX+PLUS II system directory; otherwise, it uses the /usr/maxplus2 directory. To specify a different MAX+PLUS II system directory with the ALT_HOME environment variable, you can either edit the .cshrc file to specify the correct directory or type the following command at the UNIX prompt:

    setenv ALT_HOME <MAX+PLUS II system directoryEnter

  2. Once you have synthesized your design with Design Compiler or FPGA Compiler, generate an hierarchical EDIF netlist file for the top-level design by typing the following command at the dc_shell prompt:

    write -f edif -hierarchy <top-level design name> -o <top-level design name>.hier.edf Enter

  3. Generate intermediate ACF files (.iacf) for all subdesigns that have constraints, including the top-level design.

    1. Generate the following input files for the gen_iacf utility by using a gen_iacf.cmd file. Figure 1 shows a sample gen_iacf.cmd file.

      • Flattened EDIF netlist file
      • dc_shell script file
      • Standard Delay Format (SDF) constraints construct
      • SDF timing delay construct

      Note: The gen_iacf and gen_hacf utilities do not support set_arrival timing constraints for internal nodes.

      Figure 1. Sample gen_iacf.cmd File

      ungroup -flatten -all
      write -f edif
      write_script > <design_name> + "_setup.dc"
      write_constraints -format sdf -cover_design
      write_timing -format sdf

      Note: This sample command file assumes that the design_name variable has been set before the command file is included.

    2. Run the gen_iacf utility for each design that has timing constraints (including the top-level design) by typing the following command at the UNIX prompt:

      gen_iacf <design name> Enter

  4. Rename the top-level hierarchichal EDIF netlist file to <top-level design name>.edf, if you have not already done so.

  5. Use the gen_hacf utility to merge the .iacf files for the top-level design and subdesigns into a single hierarchical ACF file, called <top level design name>.acf. Type the following command at the dc_shell prompt to start the gen_hacf utility and merge the files:

    gen_hacf <top-level design name>[<sub-design file list>] Enter


Figure 2 shows a sample dc_shell script, which includes all of the steps for using the gen_iacf and gen_hacf utilities.

Figure 2. Sample Script for Running the gen_iacf and gen_hacf Utilities

/* Sample dc_shell script for converting hierarchical
Synopsys timing constraints to the ACF format
The example design TOP has 3 lower-level
subdesigns - LOWER1, LOWER2, LOWER3.  Only
LOWER1, LOWER2 and TOP designs have constraints. */

link_library		= flex10k-3.db
target_library		= flex10k-3.db
synthetic_library	= flex10k-3.sldb

read -f vhdl LOWER1.vhd
read -f vhdl LOWER2.vhd
read -f vhdl LOWER3.vhd
read -f vhdl TOP.vhd

elaborate LOWER1
current_design=LOWER1

/* Include user-defined timing constraints for LOWER1 */

include timing1.cmd		
compile 
design_name=LOWER1

/* generate input files for gen_iacf */

include /usr/maxplus2/synopsys/bin/gen_iacf.cmd	

/* generate an intermediate ACF (.iacf) file for LOWER1 design */

sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER1

elaborate LOWER2
current_design=LOWER2

/* Include user-defined timing constraints for LOWER2 */

include timing2.cmd		
compile 
design_name=LOWER2

/* generate input files for gen_iacf */

include /usr/maxplus2/synopsys/bin/gen_iacf.cmd	

/* generate an intermediate ACF (.iacf) file for LOWER2 design */

sh /usr/maxplus2/synopsys/bin/gen_iacf LOWER2

elaborate TOP
current_design=TOP

/* Include user-defined timing constraints for TOP */

include timing3.cmd		
compile 

/* generate a hierarchical EDIF netlist file for
the top-level design before it is flattened by
the gen_iacf.cmd utility */

write -f edif -hierarchy TOP -o TOP.hier.edf

design_name=TOP

/* generate input files for gen_iacf */

include /usr/maxplus2/synopsys/bin/gen_iacf.cmd	

/* generate an intermediate ACF (.iacf) file for design TOP */

sh /usr/maxplus2/synopsys/bin/gen_iacf TOP

/* Rename the hierarchical EDIF netlist file generated
earlier to <top level design>.edf, which is required by
gen_hacf utility and MAX+PLUS II */

sh mv TOP.hier.edf TOP.edf

/* Merge all .iacf files to generate the final top-level ACF
File subdesign.list in the following command lists the names
of subdesigns that have timing constraints, one per line.
In this example it has 2 lines, one each for LOWER1 and LOWER2.
Top-level design name should not be specified in this file. */

sh /usr/maxplus2/synopsys/bin/gen_hacf TOP subdesign.list  

quit

Note: The gen_iacf utility cannot support maximum Clock frequency (fMAX) correctly if more than one Clock skew is specified in the dc_shell command script. This problem occurs because the Synopsys write_script command drops the Clock skew information for the registers. The gen_iacf utility will use the last Clock skew number to calculate fMAX.

All timing assignments generated by the gen_iacf utility are written to the Timing Requirement Assignments Section of the project's ACF, with the assignment source identifier {synopsys} at the end of each line. Figure 4 shows a sample ACF excerpt that contains Synopsys timing constraints generated by the gen_iacf utility.

Figure 4. Sample ACF Excerpt with Synopsys Timing Constraints

TIMING_POINT 
BEGIN
   "|OUT2"    : TCO = 15.00ns {synopsys};
   "|IN1"     : TPD = 10.00ns {synopsys};
   "|IN2"     : TPD = 5.00ns {synopsys};
   "|OUT1"    : TCO = 20.00ns {synopsys};
   "|IN1"     : TSU = 20.00ns {synopsys};
   "|IN2"     : TSU = 117.00ns {synopsys};
   "|CLK"     : FREQUENCY = 50.00ns {synopsys};
   "|n10_reg" : FREQUENCY = 100.00ns {synopsys};
END;

Note: The MAX+PLUS II Compiler flattens the design internally before compiling it, which may convert some of the ports on the sub-designs into internal or buried nodes. In addition, the gen_iacf and gen_hacf utilities will correctly pass tCO and tPD assignments made at lower levels of hierarchy to the ACF, but the MAX+PLUS II Compiler will ignore them and generate one or more warning messages (e.g., Warning: Ignored timing assignment for tsu|tpd|tco on buried node |TIME_STATE_MACHING:U1|tb1_3:U115|:30). In addition, hierarchical timing constraints may result in duplicate assignments in the ACF, and the MAX+PLUS II Compiler could generate an additional warning (e.g., Warning: Ignored redefinition of resources assignment (logic option assignment) for node 'CLK' Processing . . . ).
Last Updated: JAugust 28, 2000 for MAX+PLUS II version 10.0
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