Entering Resource Assignments
The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects.
Resource assignments are used to assign logic functions to a particular
pin, logic cell, I/O cell, embedded cell, row, column, Logic Array
Block (LAB), Embedded Array Block (EAB), chip, clique, local routing,
logic option, timing requirement, or connected pin group. In the MAX+PLUS
II software, you can enter all types of resource and device assignments
with Assign menu commands. You can also enter pin, logic cell,
I/O cell, embedded cell, LAB, EAB, row, and column assignments
in the MAX+PLUS II Floorplan Editor. The Assign menu commands
and the Floorplan Editor all save assignment information in the
ASCII Assignment & Configuration File (.acf)
for the project.
In designs targeted for the Synopsys Design Compiler and FPGA Compiler software,
you can assign a limited subset of these resource assignments
by setting attributes in the VHDL or Verilog HDL design files with the set_attribute command. These attributes are incorporated
into the EDIF netlist file(s). The MAX+PLUS II software automatically converts
assignment information from the EDIF Input File (.edf) into the ACF format.
For information on making MAX+PLUS II-compatible resource assignments with the set_attribute command, go to the following topics:
You can also modify the ACF for a design to contain timing requirements and other assignments, as described in the following topics:
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| Refer to the following sources for related information:
- Synopsys documentation for additional information on how to assign properties
- "Resource Assignments in EDIF Input Files" and "Assigning
Resources in a Third-Party Design Editor" in MAX+PLUS II
Help for more information on assignments or properties that can
be assigned in Synopsys
- "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu), for information on entering assignments
in the MAX+PLUS II software with Assign menu commands or in an ACF
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