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Using the Max2 Express Drawer's VHDL <-> max2 UtilityOnce you have created a VHDL Design File (.vhd) for your project, you can use the VHDL <-> max2 utility in the Max2 Express drawer to synthesize and optimize the design; generate an EDIF netlist file; and process the EDIF netlist file with the MAX+PLUS II Compiler to generate an EDIF Output File (.edo) for simulation. The VHDL <-> max2 utility creates all necessary subdirectories and copies all files to the correct locations. To use the VHDL <-> max2 utility, follow these steps:
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||