August 28, 2000 for MAX+PLUS II version 10.0
MAX+PLUS II ACCESS Key Guidelines
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Using Cadence RapidSIM & MAX+PLUS II Software

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The following topics describe how to use the Cadence RapidSIM software with MAX+PLUS® II software. Click on one of the following topics for information:

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Setting Up the MAX+PLUS II/Cadence Working Environment

  • Software Requirements
  • MAX+PLUS II Directory Structure
  • MAX+PLUS II/Cadence Interface File Organization
  • Concept & RapidSIM Local Work Area Directory Structure

Simulation

  • Project Simulation Flow
  • Performing a Timing Simulation with RapidSIM Software
Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information:
  • Compiling Projects with MAX+PLUS II Software
  • Programming Altera Devices

 

Go to the following topics, which are available on the web, for additional information:

  • MAX+PLUS II Development Software
  • Altera Programming Hardware
  • Cadence web site (http://www.cadence.com)


Setting Up the MAX+PLUS II/Cadence Working Environment

To use MAX+PLUS® II software with Cadence software, you must first install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Cadence interface is installed automatically when you install the MAX+PLUS II software on your computer. Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Cadence Interface File Organization for information about the MAX+PLUS II/Cadence directories that are created during MAX+PLUS II installation.

NOTE: The information presented here assumes that you are using the C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Cadence interface, follow these steps:

  1. Ensure that you have correctly installed the MAX+PLUS II and Cadence software versions described in the MAX+PLUS II/Cadence Software Requirements.

  2. Add the following environment variables to your .cshrc file:

    setenv ALT_HOME /usr/maxplus2 Enter

    setenv CDS_INST_DIR <Cadence system directory path> Enter

  3. Add the $ALT_HOME/cadence/bin and $CDS_INST_DIR/tools/bin directories to the PATH environment variable in your .cshrc file. Make sure these paths are placed before the Cadence hierarchy path.

  4. Add /usr/dt/lib and /usr/ucb/lib to the LD_LIBRARY_PATH environment variable in your .cshrc file.

  5. Create a new cds.lib file in your working directory or edit an existing one so that it includes all of the following lines that apply to the Cadence tools you have installed:

    DEFINE alt_syn ${ALT_HOME}/simlib/concept/alt_syn

    DEFINE lpm_syn ${ALT_HOME}/simlib/concept/lpm_syn

    DEFINE alt_lpm ${ALT_HOME}/simlib/concept/alt_lpm

    DEFINE alt_mf ${ALT_HOME}/simlib/concept/alt_mf

    DEFINE alt_max2 ${ALT_HOME}/simlib/concept/alt_max2

    DEFINE alt_max2 ${ALT_HOME}/simlib/composer/alt_max2/alt_max2

    DEFINE alt_vtl $ALT_HOME/simlib/concept/alt_vtl/lib

    DEFINE altera $ALT_HOME/simlib/concept/alt_mf/lib

    SOFTINCLUDE $CDS_INST_DIR/tools/leapfrog/files/cds.lib

    DEFINE <design name>.

  6. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:

    cp /usr/maxplus2/maxplus2.ini $HOME Enter

    chmod u+w $HOME/maxplus2.ini Enter

    Note:

    The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as MAX+PLUS II symbol and logic function library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.

    Normally, you do not have to edit your local copy of maxplus2.ini because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

  7. If you are using Concept on a Sun SPARCstation running SunOS, go to Setting Up the MAX+PLUS II/Cadence Concept Work Environment for a Sun SPARCstation Running SunOS Software to install the redifnet EDIF netlist reader utility.

  8. If you are using Synergy software, edit the hdl.var file located in your working directory to include the following line:

    DEFINE work <design name> Enter

  9. Set up an appropriate directory structure for the tool(s) you are using. See the following topics for information:

    • Composer Project File Directory Structure
    • Concept & RapidSIM Local Work Area Directory Structure

Go to: Go to the following topics, which are available on the web, for additional information:
  • MAX+PLUS II Getting Started version 8.1 (5.4 MB)
  • This manual is also available in 4 parts:
    • Preface & Section 1: MAX+PLUS II Installation
    • Section 2: MAX+PLUS II - A Perspective
    • Section 3: MAX+PLUS II Tutorial
    • Appendices, Glossary & Index


MAX+PLUS II Directory Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, Verilog HDL, or VHDL netlist file; an AHDL Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by the altout or concept2alt utility and imported into the MAX+PLUS II software as an EDIF Input File (.edf).

Project design files and output files are stored in the project directory, with the exception of standard library functions provided by Altera or another EDA tool vendor. The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all design files in a project hierarchy.


MAX+PLUS II/Cadence Interface File Organization

Table 1 shows the MAX+PLUS® II/Cadence interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation. For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

Table 1. MAX+PLUS II Directory Organization

Directory
Description
./lmf Contains the Altera-provided Library Mapping File, cadence.lmf, that maps Cadence logic functions to equivalent MAX+PLUS II logic functions.
./examples/cadence Contains the sample files for Cadence software discussed in these ACCESSSM Key Guidelines.
./cadence Contains the AMPLE userware for the MAX+PLUS II/Cadence interface.
./simlib/concept/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX® 6000 devices only) for use with Concept software.
./simlib/composer/alt_max2 Contains the MAX+PLUS II primitives, including CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE (D flipflop with Clock Enable), and DFFE6K (D flipflop with Clock Enable and both Clear and Preset for FLEX 6000 devices only) for use with Composer software.
./simlib/concept/alt_lpm Contains the MAX+PLUS II megafunctions, including library of parameterized modules (LPM) functions, for use with Concept software.
./simlib/concept/max2sim Contains the MAX+PLUS II/Concept simulation model library, max2_sim, for use with RapidSIM software.
./simlib/concept/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Concept software, and the vlog2alt utility.
./simlib/composer/alt_syn Contains the MAX+PLUS II synthesis library, alt_syn, for use with Synergy and Composer software.
./simlib/concept/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Concept software.
./simlib/composer/lpm_syn Contains the Cadence LPM library, lpm_syn, for use with Synergy and Composer software.
./simlib/concept/alt_mf Contains the MAX+PLUS II VHDL logic function library. (a_8count is for the MAX® 7000 and MAX 9000 device families only.)
./simlib/concept/edifnet/templates Contains template files for Concept directives, i.e., global.cmd, compiler.cmd, vloglink.cmd, verilog.cmd, and master.local.
./simlib/concept/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Concept software.
./simlib/composer/alt_max2/verilogUdps Contains Verilog HDL modules that are the equivalent of the primitives contained in alt_max2 library for use with Composer software.
./simlib/concept/alt_vtl
./simlib/composer/alt_vtl
Contains VITAL library source files for use with Concept or Composer software.
./simlib/composer/alt_max2/verilog Contains simulation modules for all symbols in the alt_max2 Composer library.

Go to: Go to the following topics, which are available on the web, for additional information:
  • MAX+PLUS II Getting Started version 8.1 (5.4 MB)
  • This manual is also available in 4 parts:
    • Preface & Section 1: MAX+PLUS II Installation
    • Section 2: MAX+PLUS II - A Perspective
    • Section 3: MAX+PLUS II Tutorial
    • Appendices, Glossary & Index
  • FLEX Devices
  • MAX Devices
  • Classic Device Family


Concept & RapidSIM Local Work Area Directory Structure

When the redifnet utility imports an EDIF netlist file for the RapidSIM software, it creates a SCALD directory for your project. However, creating this directory may overwrite the directory that was created for the original Concept schematic. To prevent overwriting this directory, you should create a file structure that helps you manage your design files.

Altera recommends that you create the following three directories for your design files.

Directory: Description:
 
./source Create Concept schematics and generate EDIF netlist files with the wedifnet utility in the source directory.
./max2 Copy the EDIF Input File (.edf) from the source directory to this directory to compile the file with the MAX+PLUS® II software.
./dest Copy the EDIF Output File (.edo) from the max2 directory to this directory to run the redifnet and RapidSIM software.

Copies of the appropriate directives files for Cadence tools must be present in both the source and dest directories. Figure 1 shows Altera's recommended file structure.

Figure 1. Recommended File Structure

Figure 1


Project Simulation Flow

Figure 1 shows the project simulation flow for the MAX+PLUS® II/Cadence interface.

Figure 1. MAX+PLUS II/Cadence Project Simulation Flow

Altera-provided items are shown in blue.

Figure 1


Performing a Timing Simulation with RapidSIM Software

You can use the Cadence redifnet utility to read MAX+PLUS® II-generated EDIF Output Files and prepare them for timing simulation with RapidSIM software. RapidSIM software can simulate both the functionality and the timing of your design. It also checks setup time requirements, hold time requirements, and Clock duty cycle timing requirements on registers.

To simulate projects with RapidSIM software, follow these steps:

  1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Cadence Working Environment.

  2. Generate an EDIF Output File (.edo), as described in Compiling Projects with MAX+PLUS II Software.

  3. Copy the EDIF Output File <file name>.edo from the /<working directory>/max2 directory to the /<working directory>/dest directory.

  4. Convert the EDIF Output File into the SCALD project format by typing redifnet <design name> Enter at the UNIX prompt from the /<working directory>/dest directory.

  5. Type lwb_rapidsim Enter at the UNIX prompt to generate the global.cmd directive file.

  6. Choose the RapidSIM button from the Logic Workbench window to start RapidSIM and simulate your EDIF Output File.


Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

Note: Refer to the following sources for additional information:

  • Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

  • Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

  1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

  2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

    Note: Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

  3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

    Note: You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type setacf -h Enter and maxplus2 -h Enter for descriptions of setacf and MAX+PLUS II command-line syntax.

  4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

  5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

    1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

    2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      Note: If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

    3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

    4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than VCC or GND for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

    5. Choose OK.

  6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

  7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:

    • Exemplar Logic Galileo Extreme-Specific Compiler Settings
    • Synopsys DesignWare-Specific Compiler Settings
    • Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
    • Synplicity Synplify-Specific Compiler Settings

  8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

    1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      Note: This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

    2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

    3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

    4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

  9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

    Note: See step 3 for information on running MAX+PLUS II software from the command line.

  10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

  • JEDEC Files (.jed)
  • Programmer Object Files (.pof)
  • SRAM Object Files (.sof)
  • Hexadecimal (Intel-format) Files (.hex)
  • Tabular Text Files (.ttf)
Go to: Refer to the following sources for additional information:
  • Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
  • Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
  • Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
  • Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

 

Go to the following topics, which are available on the web, for additional information:

  • MAX+PLUS II Development Software
  • Altera Programming Hardware


Programming Altera Devices

Once you have successfully compiled and simulated a project with the MAX+PLUS® II software, you can program an Altera® device and test it in the target circuit. Figure 1 shows the device programming flow for MAX+PLUS II software.

Figure 1. MAX+PLUS II Device Programming Flow

Altera-provided items are shown in blue.

Figure 1

You can program devices with Altera programming hardware and MAX+PLUS II Programmer software installed on a 486- or Pentium-based PC or a UNIX workstation, or with programming hardware and software available from other manufacturers. Table 1 shows the available Altera programming hardware options on PCs and UNIX workstations.

Table 1. Altera Programming Hardware
Programming
Hardware
Option
PCs
UNIX
Work-
stations
ACEX® 1K
Devices
MAX® 3000A
Devices
Classic®
&
MAX 5000
Devices
MAX 7000
&
MAX 7000E
Devices

MAX 7000A,
MAX 7000AE,
MAX 7000B,
MAX 7000S
MAX 9000
&
MAX 9000A
Devices

FLEX® 6000,
FLEX 6000A,
FLEX 8000,
FLEX 10K,
FLEX 10KA,
FLEX 10KB,
&
FLEX 10KE Devices
In-System
Programming/
Configuration
Logic Programmer
card, PL-MPU
Master
Programming
Unit, and
device-specific
adapters
Step:
   
Step:
Step:
Step:
Step:
   
BitBlaster
Download Cable
Step:
Step:
Step:
Step:
   
Step:
Step:
Step:
ByteBlasterMV
Download Cable
Step:
 
Step:
Step:
   
Step:
Step:
Step:
MasterBlaster Download Cable
Step:
Step:
Step:
Step:
   
Step:
Step:
Step:

If you wish to transfer programming files from a UNIX workstation to a PC over a network with File Transfer Protocol (FTP) or other similar transfer programs, be sure to select binary transfer mode.

Programming hardware from other manufacturers varies, but typically consists of a device connected to one of the serial ports on the workstation. Various vendors, such as Data I/O and BP Microsystems, supply hardware and software for programming Altera devices.

Go to: Go to Compiling Projects with MAX+PLUS II Software for information on creating programming files.

 

Go to the following topics, which are available on the web, for additional information:

  • MAX+PLUS II Development Software
  • Altera Programming Hardware
  • FLEX Devices
  • MAX Devices
  • Classic Device Family

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