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Altera VHDL & Verilog HDL alt_mf Logic Function LibraryThe alt_mf library contains behavioral VHDL and Verilog HDL models of the
The behavioral descriptions of these four functions are contained in the /usr/maxplus2/synopsys/library/alt_mf/src directory, which contains the following files:
If you wish to simulate a VHDL design containing these logic functions, you can use the Altera-provided shell script analyze_vss to create a design library called altera. This library allows you to reference the functions through the VHDL Library and Use Clauses, which direct the Design Compiler or FPGA Compiler software to incorporate the library files when it compiles your top-level design file. The analyze_vss shell script creates the altera design library by analyzing the VHDL System Simulator (VSS) simulation models in the /usr/maxplus2/synopsys/library/alt_mf/lib directory. See Setting Up VSS Configuration Files for more information on using the analyze_vss shell script. Complete VHDL and Verilog HDL behavioral descriptions of these logic functions are included in the mf.vhd and mf.v files so that you can optionally retarget your design to other technology libraries. |
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||||||||||||||||||||||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||||||||||||||||||||||||