Using ViewDraw & ViewGen Software to Prepare for Multi-Device Board-Level Simulation with ViewSim Software
In order to perform board-level simulation with ViewSim software, you must generate symbols that represent each MAX+PLUS® II-generated EDIF Output File (.edo) and incorporate them into a top-level ViewDraw schematic. You can use ViewGen to generate hollow-body symbols to represent each EDIF Output File, and connect them to other system components in the top-level schematic. You must also edit the wirelist files (.wir) created by the edifneti utility.
To prepare for multi-device board-level simulation with ViewSim software, follow these steps:
- Perform steps 1 through 6c in Performing a Timing Simulation with ViewSim Software.
- Start ViewGen by double-clicking Button 1 on the max2_VGen icon in the Design Tools Drawer.
- Specify the filename of one of the EDIF Output Files <filename>.edf in the Name box in the ViewGen dialog box and choose OK to generate a corresponding <filename> symbol.
- Repeat step 3 to generate other symbols as needed. You do not need to generate a symbol for the <filename>_t.edf file.
- Eliminate the two extra pins for
VDD and GND connections from the top-level wirelist file ./wir/<design name>_t.1:
- Open the ./wir/<design name>_t.1 wirelist file with a standard text editor and delete the following lines:
P IN GND
I GND IN GND
P IN VDD
I VDD IN VDD
- Add the following two lines to the file to ensure global ground and power connections for simulation:
G VDD
G GND 
- Save the top-level wirelist file with your changes.
- Continue with the steps necessary to perform timing simulation, as described in Performing a Timing Simulation with ViewSim Software.
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