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Using ACFs Generated by FPGA Express SoftwareWith FPGA Express software, you can either generate a new Assignment & Configuration File (.acf), along with an EDIF netlist file (.edf) and Library Mapping File (.lmf), to be imported into the
The ACF incorporates the following assignments from FPGA Express software and passes them to the MAX+PLUS II software:
Figure 1 shows an example of a typical ACF generated by the FPGA Express software. Figure 1. FPGA Express-Generated Assignment & Configuration File CHIP my_chip
DEVICE = EPF10K100GC503-3 {synopsys};
"|_CONFIG" : PIN = P40 {synopsys};
"|_STATUS" : PIN = P41 {synopsys};
GLOBAL_PROJECT_SYNTHESIS_ASSIGNMENT_OPTIONS
DEVICE_FAMILY = FLEX10K {synopsys};
STYLE = WYSIWYG {synopsys};
OPTIMIZE_FOR_SPEED = 5 {synopsys};
AUTO_GLOBAL_CLOCK = ON {synopsys};
LOGIC_OPTIONS
"|TX_FIFOA_D6" : IO_CELL_REGISTER = ON {synopsys};
"|DEST_RAM_D6" : SLOW_SLEW_RATE = ON {synopsys};
"|DEST_RAM_D5" : SLOW_SLEW_RATE = OFF {synopsys};
COMPILER_INTERFACES_CONFIGURATION
EDIF_INPUT_VCC = VDD {synopsys};
EDIF_INPUT_GND = GND {synopsys};
EDIF_INPUT_USE_LMF1 = ON {synopsys};
EDIF_INPUT_LMF1 = "my_chip.lmf" {synopsys};
TIMING_POINT
FREQUENCY = 50MHz {synopsys};
"CLK80" : FREQUENCY = 80MHz {synopsys};
"G" : FREQUENCY = 25MHz {synopsys};
TPD = 10ns {synopsys};
"inp1" : TSU = 20ns {synopsys};
"out1" : TCO = 15ns {synopsys};
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||
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Copyright © 2000 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |||||