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Entering Resource AssignmentsThe Concept & Composer SchematicsIn both Concept and Composer schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:
Go to the Cadence Concept Schematic User Guide and Composer Reference User Guide for details on how to assign properties. Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Concept and Composer. Installing the Altera-provided MAX+PLUS II/Cadence interface on your computer automatically creates the following sample Concept and Composer schematic files, which include resource assignments:
VHDL & Verilog HDL Design FilesFor Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. For information on using the setacf utility, go to Modifying the Assignment & Configuration File with the setacf Utility.
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| Last Updated: August 28, 2000 for MAX+PLUS II version 10.0 | |||||
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