MAX+PLUS II ACCESS Key Guidelines
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Using Mentor Graphics Design Architect & MAX+PLUS II Software

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The following topics describe how to use the Mentor Graphics Design Architect software with MAX+PLUS® II software. Click on one of the following topics for information:

This file is suitable for printing only. It does not contain hypertext links that allow you to jump from topic to topic.

Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

  • Software Requirements
  • Altera-Provided Logic & Symbol Libraries
  • Local Work Area Directory Structure
  • Mentor Graphics Project Directory Structure
  • MAX+PLUS II Project Directory Structure
  • MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

Design Entry

  • Design Entry Flow
  • Creating Design Architect Schematics for Use with MAX+PLUS II Software
    • Instantiating the clklock Megafunction in Design Architect Schematics
    • Instantiating LPM Functions in Design Architect Schematics
  • Entering Resource Assignments
    • Assigning Pins, Logic Cells & Chips
    • Assigning Cliques
    • Assigning Logic Options
    • Modifying the Assignment & Configuration File with the setacf Utility
  • Creating Hierarchical Projects with Design Architect Software
  • Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility

Simulation

  • Performing a Functional Simulation with DVE & QuickSim II Software
  • Performing a Functional Simulation with QuickHDL Pro Software

Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information.
  • Compiling Projects with MAX+PLUS II Software
  • Programming Altera Devices

 

Go to the following topics, which are available on the web, for additional information:

  • MAX+PLUS II Development Software
  • Altera Programming Hardware
  • Mentor Graphics web site (http://www.mentor.com)


Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment

To use the MAX+PLUS® II software with Mentor Graphics/Exemplar Logic software, you must install the MAX+PLUS II software, then establish an environment that facilitates entering and processing designs. The MAX+PLUS II/Mentor Graphics/Exemplar Logic interface is installed automatically when you install the MAX+PLUS II software on your computer.

Go to MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual for more information on installation and details on the directories that are created during MAX+PLUS II installation. Go to MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization for information about the MAX+PLUS II/Mentor Graphics directories that are created during MAX+PLUS II installation.

Note: The information presented here assumes that you are using a C shell and that your MAX+PLUS II system directory is /usr/maxplus2. If not, you must use the appropriate syntax and procedures to set environment variables for your shell.

To set up your working environment for the MAX+PLUS II/Mentor Graphics interface, follow these steps:

  1. Ensure that you have correctly installed the MAX+PLUS II and Mentor Graphics software versions described in MAX+PLUS II/Mentor Graphics Software Requirements.
  2. Add the following environment variables to your .cshrc file:
  3. setenv ALT_HOME /usr/maxplus2 Enter
    setenv MGC_WD <user-specified working directory> Enter
    setenv MGC_HOME <Mentor Graphics system directory> Enter
    setenv MAX2_MENTOR /usr/maxplus2/mentor/max2 Enter
    setenv MGC_LOCATION_MAP <user-specified location_map file> Enter
    setenv EXEMPLAR <Galileo or Leonardo system directory> Enter

    Note: Installing the Altera®­provided MAX+PLUS II/Mentor Graphics interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/.cshrc file.

  4. Add the $MGC_HOME/bin, $MAX2_MENTOR/bin, $ALT_HOME/bin, $EXEMPLAR/bin/<os>, and $ALT_HOME/bin directories to the PATH environment variable in your .cshrc file, where <os> is the operating system, e.g., SUN4 for SunOS; SUN5 for Solaris.
  5. If you plan to use the Altera Schematic Express (sch_exprss) utility or the Altera VHDL Express (vhd_exprss) utility, add the following environment variable to your .cshrc file:
  6. setenv MAX2_QSIM /usr/maxplus2/simlib/mentor/max2sim Enter

  7. Type source ~/.cshrc at a UNIX prompt to source the .cshrc file and validate the settings in steps 1 through 4.
  8. Add the following lines to your MGC_location_map file:
  9. $MAX2_MENTOR Enter
    /usr/maxplus2/mentor/max2 Enter
    $MGC_GENLIB Enter
    /<user-specified Mentor Graphics GEN_LIB directory> Enter
    $MGC_LSLIB Enter
    /<user-specified Mentor Graphics LS_LIB directory> Enter
    $MAX2_EXAMPLES Enter
    /<user-specified example directory> Enter
    $MAX2_LMCLIB Enter
    /<user-specified Logic Modeling directory> Enter
    $MAX2_GENLIB Enter
    /usr/maxplus2/simlib/mentor/alt_max2 Enter
    $MAX2_QSIM Enter
    /usr/maxplus2/simlib/mentor/max2sim Enter
    $MAX2_FONT Enter
    /usr/maxplus2/mentor/max2/fonts Enter
    $MGC_SYS1076_STD Enter
    /<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ std Enter
    $MGC_SYS1076_ARITHMETIC Enter
    /<user-specified MGC_HOME directory>/pkgs/sys_1076_std/arithmetic Enter
    $MGC_SYS1076_PORTABLE Enter
    /<user-specified MGC_HOME directory>/pkgs/sys_1076_std/mgc_portable Enter
    $MGC_SYS1076_IEEE Enter
    /<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ieee Enter
    $MGC_SYS1076_SRC Enter
    /<user-specified MGC_HOME directory>/pkgs/sys_1076_std/ src Enter
    $MAX2_MFLIB Enter
    /usr/maxplus2/simlib/mentor/alt_mf Enter

    Note: Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically installs a template for these environment variables in the /usr/maxplus2/mentor/max2/location_map/location_map file.

  10. If you want to use QuickHDL software to simulate VHDL or Verilog HDL designs, add the following line in the [library] section of your quickhdl.ini file: altera = $MAX2_MFLIB.
  11. If you plan to use QuickHDL software to simulate VITAL-compliant VHDL files, add the following lines to your MGC_location_map file:
  12. $MAX2_VTLLIB Enter
    /usr/maxplus2/simlib/mentor/alt_vtl Enter

  13. Copy the /usr/maxplus2/maxplus2.ini file to your $HOME directory:
  14. cp /usr/maxplus2/maxplus2.ini $HOME Enter
    chmod u+w $HOME/maxplus2.ini Enter

    Note: The maxplus2.ini file contains both Altera- and user-specified initialization parameters that control the MAX+PLUS II software, such as Altera­provided logic and symbol library paths and the current project name. The MAX+PLUS II installation procedure creates and copies the maxplus2.ini file to the /usr/maxplus2 directory.

    Normally, you do not have to edit your local copy of maxplus2.ini, because the MAX+PLUS II software updates the file automatically whenever you change any parameters or settings. However, if you move the max2lib and max2inc library subdirectories, you must update the file. Go to "Creating & Using a Local Copy of the maxplus2.ini File" in MAX+PLUS II Help for more information.

Go to: Go to the following topics, which are available on the web, for additional information:
  • MAX+PLUS II Getting Started version 8.1 (5.4 MB)
  • This manual is also available in 4 parts:
    • Preface & Section 1: MAX+PLUS II Installation
    • Section 2: MAX+PLUS II - A Perspective
    • Section 3: MAX+PLUS II Tutorial
    • Appendices, Glossary & Index


MAX+PLUS II/Mentor Graphics Software Requirements

The following products are used to generate, process, synthesize, and verify a project with the MAX+PLUS® II software and Mentor Graphics software:

Mentor Graphics
Exemplar
Altera
version C.2:
System_1076 Compiler
QuickSim II
Design Architect
ENRead
ENWrite
GEN_LIB library
QuickHDL
QuickHDL Pro
QuickPath
LS_LIB library (optional)
DVE

Leonardo Spectrum version 2000.1b
MAX+PLUS II
version 10.0

Note: The MAX+PLUS II read.me file provides up-to-date information on which versions of Mentor Graphics applications are supported by the current version of MAX+PLUS II. It also provides information on installation and operating requirements. You should read the read.me file on the CD-ROM before installing the MAX+PLUS II software. After installation, you can open the read.me file from the MAX+PLUS II Help menu.


Altera-Provided Logic & Symbol Libraries

The MAX+PLUS® II/Mentor Graphics environment provides libraries for compiling, synthesizing, and simulating designs.

Note: You can create your own libraries of custom functions for use in Design Architect schematics and VHDL and Verilog HDL design files. You can use custom functions to incorporate an EDIF Input File (.edf), Text Design File (.tdf), or any other MAX+PLUS II-supported design file into a project. The MAX+PLUS II software uses the Altera®­provided mnt8_bas.lmf and exemplar.lmf Library Mapping Files to map standard Design Architect symbols and VHDL and Verilog HDL functions to equivalent MAX+PLUS II logic functions. To use custom functions, you can create a custom LMF that maps your custom functions to the equivalent EDIF input file, TDF, or other design file. Go to "Library Mapping File" in MAX+PLUS II Help for more information.

Design Architect Libraries

You can enter a Design Architect schematic with logic functions from these Altera-provided symbol libraries: ALTERA LPMLIB, ALTERA GENLIB, LSTTL BY TYPE, and LSTTL ALL PARTS. You can access these libraries by choosing Altera Libraries (Libraries menu) in the Design Architect software. For information on using library of parameterized modules (LPM) functions, see ALTERA LPMLIB Library below.

ALTERA GENLIB Library (Design Architect) & Altera (VHDL) Libraries

The ALTERA GENLIB symbol library (called the Altera library for VHDL) includes several MAX+PLUS II primitives for controlling design synthesis and fitting. It also includes four macrofunctions (8count, 8mcomp, 8fadd, and 81mux) that are optimized for different Altera device families, and the clklock phase-locked loop megafunction, which is supported for some FLEX® 10K devices.

The following table shows the MAX+PLUS II-specific logic functions.

Table 1. MAX+PLUS II-Specific Logic Functions
Macrofunctions Note (1)
Primitives
Name
Description
Name
Description
Name
Description
8fadd 8-bit full adder LCELL Logic cell buffer EXP MAX® 5000, MAX 7000, and MAX 9000 Expander buffer
8mcomp 8-bit magnitude comparator GLOBAL Global input buffer SOFT Soft buffer
8count 8-bit up/down counter CASCADE FLEX 6000, FLEX 8000, and FLEX 10K cascade buffer OPNDRN Open-drain buffer
81mux 8-to-1 multiplexer CARRY FLEX 6000, FLEX 8000, and FLEX 10K carry buffer DFFE DFFE6K
Note (2)
D-type flipflop with Clock Enable
clklock Phase-locked loop

Notes:

  1. Logic function names that begin with a number must be preceded by "a_" in VHDL designs. For example, 8fadd must be specified as a_8fadd instead.
  2. If you want to use QuickHDL software, make sure you have updated your quickhdl.ini file, as described in step 7 of Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
  3. For designs that are targeted for FLEX 6000 devices, you should use the DFFE primitive only if the design contains either a Clear or Preset signal, but not both. If your design contains both a Clear and a Preset signal, you must use the DFFE6K primitive.

Note: Choose Old-Style Macrofunctions, Primitives, or Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on these functions.

ALTERA LPMLIB Library

The Altera­provided ALTERA LPMLIB library, which is available for Design Architect schematics and VHDL designs, includes standard functions from the library of parameterized modules (LPM) 2.1.0, except the truth table, finite state machine, and pad functions. The LPM standard defines a set of parameterized modules (i.e., parameterized functions) and their corresponding representations in an EDIF netlist file. These logic functions allow you to create and functionally simulate an LPM-based design without targeting a specific device family. After the design is completed, you can target the design to any device family. The parameters you specify for each LPM function determine which simulation models are generated.

Note: Choose Megafunctions/LPM from the MAX+PLUS II Help menu for more information about LPM functions.

Go to:

Go to the following topics, which are available on the web, for additional information:

  • FLEX Devices
  • MAX Devices
  • Classic Device Family


Local Work Area Directory Structure

Design Architect software automatically creates and maintains the project directory structure required for all stages of design entry. Galileo Extreme, Leonardo, and ENWrite software create a max2 subdirectory, if it does not already exist, under the project directory. These software applications also generate EDIF netlist files, and copy them from the <project name> directory to this max2 subdirectory. All MAX+PLUS® II Compiler output files are created in the max2 subdirectory.

Simulation files created with Mentor Graphics applications and Logic Modeling files are located in the board-level simulation subdirectory of the project directory. You can use these files during simulation with QuickSim II software.

The only directory you need to create is the local work directory, which should contain all project directories. Figure 1 shows the recommended file structure.

Figure 1. Recommended File Structure

Recommended File Structure

Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information:
  • MAX+PLUS II Project Directory Structure
  • Mentor Graphics Project Directory Structure


Mentor Graphics Project Directory Structure

Design Architect software generates the following files for each schematic:

  • <drawing name>/mgc_component.attr
  • <drawing name>/part.Eddm_part.attr
  • <drawing name>/part.part_1
  • <drawing name>/schematic.mgc_schematic.attr
  • <drawing name>/schematic/schem_id
  • <drawing name>/schematic/sheet1.mgc_sheet.attr
  • <drawing name>/schematic/sheet1.sgfx_1
  • <drawing name>/schematic/sheet1.ssht_1

The files generated for each schematic are stored in the schematic's <drawing name> directory and should not be edited. Mentor Graphics software automatically manages file storage and retrieval operations through this <drawing name> directory structure, which does not reflect hierarchical design relationships. Figure 1 shows a sample file structure with project1 as the UNIX project directory, and design1, subdesign1, and subdesign2 as the directories for the top-level design and subdesigns of the project.

Figure 1. Design Architect Project File Structure

Project File Structure

When the ENWrite utility converts the schematic into an EDIF netlist file, it processes the design information and all related file subdirectories, then creates the EDIF netlist file in the directory defined by the user. The EDIF netlist file is named <project name>.edf, where <project name> is the name of the top-level design file. The <project name>.edf file is automatically moved to the max2 directory under the project directory.

Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information:
  • Local Work Area Directory Structure
  • MAX+PLUS II Project Directory Structure


MAX+PLUS II Project Directory Structure

In the MAX+PLUS® II software, a project name is the name of a top-level design file, without the filename extension. This design file can be an EDIF, VHDL, or Verilog HDL netlist file; an Altera Hardware Description Language (AHDL) Text Design File (TDF); or any other MAX+PLUS II-supported design file. The EDIF netlist file must be created by ENWrite, Galileo Extreme, or Leonardo software and imported into MAX+PLUS II as an EDIF Input File (.edf). Figure 1 shows an example of a MAX+PLUS II project directory.

Figure 1. Sample MAX+PLUS II Project Directory

MAX+PLUS II Project Directory

The MAX+PLUS II software stores the connectivity data on the links between design files in a hierarchical project in a Hierarchy Interconnect File (.hif), but refers to the entire project only by its project name. The MAX+PLUS II Compiler uses the HIF to build a single, fully flattened project database that integrates all the design files in a project hierarchy.

Go to: Go to the following MAX+PLUS II ACCESSSM Key topics for related information:
  • Local Work Area Directory Structure
  • Mentor Graphics Project Directory Structure


MAX+PLUS II/Mentor Graphics/Exemplar Logic Interface File Organization

The following table shows the MAX+PLUS® II/Mentor Graphics interface subdirectories that are created in the MAX+PLUS II system directory (by default, the /usr/maxplus2 directory) during MAX+PLUS II installation.

Go to: For information on the other directories that are created during MAX+PLUS II installation, see "MAX+PLUS II File Organization" in MAX+PLUS II Installation in the MAX+PLUS II Getting Started manual.

Table 1. MAX+PLUS II Directory Organization
Directory
Description
.lmf Contains the Altera-provided Library Mapping Files, mnt8_bas.lmf and exemplar.lmf, that map Mentor Graphics and Exemplar Logic logic functions to equivalent MAX+PLUS II logic functions.
./mentor Contains the AMPLE userware for the MAX+PLUS II/Mentor Graphics interface.
./simlib/mentor/alt_max2 Contains MAX+PLUS II primitives such as CARRY, CASCADE, EXP, GLOBAL, LCELL, SOFT, OPNDRN, DFFE, and DFFE6K (D flipflop with Clock Enable) for use in Design Architect schematics.
./simlib/mentor/max2sim Contains the MAX+PLUS II/Mentor Graphics simulation model library, max2sim, for use with QuickSim II and QuickPath software.
./simlib/mentor/synlib Contains the MAX+PLUS II synthesis library for use with AutoLogic II software, which supports synthesis for users running Mentor Graphics version B1.
./simlib/mentor/alt_mf Contains the MAX+PLUS II macrofunction and megafunction libraries.
./simlib/mentor/alt_vtl Contains the MAX+PLUS II VITAL library.


Mentor Graphics/Exemplar Logic Design Entry Flow

The following figure shows the design entry flow for the MAX+PLUS® II/Mentor Graphics/Exemplar Logic interface.

Figure 1. MAX+PLUS II/Mentor Graphics/Exemplar Logic Design Entry Flow

Altera­provided items are shown in blue.

Design Entry Flow


Creating Design Architect Schematics for Use with MAX+PLUS II Software

You can create Design Architect schematics and convert them into EDIF Input Files (.edf) that can be processed with the MAX+PLUS® II Compiler.

To create a Design Architect schematic for use with MAX+PLUS II software, go through the following steps:

  1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
  2. Start the MAX+PLUS II/Mentor Graphics interface by typing max2_dmgr Enter at a UNIX prompt.
  3. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing max2_da  at the UNIX prompt.
  4. Use the graphical user interface to structure and organize your files to create an environment that facilitates entering and processing designs. Go to the following topics for more information:
    • Local Work Area Directory Structure
    • MAX+PLUS II Project Directory Structure
    • Mentor Graphics Project Directory Structure

  5. Choose the OPEN SHEET button in the Design Architect session_palette, then specify a name for your project in the Component Name box. Choose OK.
  6. Enter logic functions from the following Altera®­provided libraries:
    • ALTERA LPMLIB includes library of parameterized modules (LPM) functions
    • ALTERA GENLIB includes primitives and macrofunctions
    • LSTTL includes 74-series macrofunctions

    Note: You can instantiate MegaCore™ functions offered by Altera or by members of the Altera Megafunction Partners Program (AMPPSM). The OpenCore™ feature in the MAX+PLUS II software allows you to instantiate, compile, and simulate MegaCore functions before deciding whether to purchase a license for full device programming and post-compilation simulation support.

    The following topics describe special steps needed to instantiate LPM and clklock functions:

    • Instantiating LPM Functions in Design Architect Schematics
    • Instantiating the clklock Megafunction in Design Architect Schematics

  7. (Optional) To create a hierarchical design that contains symbols representing other design files, such as AHDL or VHDL design files, go to Creating Hierarchical Projects with Design Architect Software.
  8. If you wish to make resource assignments in a Design Architect schematic, go to Entering Resource Assignments. You can also enter resource assignments from within the MAX+PLUS II software.
  9. Choose Check Sheet for Altera (Check menu) to save and check your design. If your design contains LPM functions , the Design Architect software will ask whether you want to compile the LPM model. Choose YES if you want to compile the VHDL code for the LPM functions. The software will automatically select the corresponding compiler: System 1076 for B.(x) releases and QuickHDL compilers for releases C.1 and later.
  10. (Optional) If your schematic design includes models for VHDL or Verilog HDL designs, perform a functional simulation with the QuickHDL Pro software, as described in Performing a Functional Simulation with QuickHDL Pro Software. If it does not, you can perform a functional simulation with the QuickSim software, as described in Performing a Functional Simulation with DVE & QuickSim II Software.
  11. Once you have created a schematic, you can generate an EDIF netlist file that can be imported into the MAX+PLUS II software with either of the following methods:
    • You can create an EDIF netlist file, as described in Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility.
    • You can use the Altera Schematic Express utility, sch_exprss, to automatically create an EDIF netlist file, compile it with the MAX+PLUS II Compiler, generate an EDIF Output File (.edo), and prepare the EDIF Output File for simulation with ENRead and Design Viewpoint Editor (DVE), as described in Using the Altera Schematic Express (sch_exprss) Utility.

    Even if your design is a hierarchical design incorporating files created with multiple design entry methods, both the ENWrite and Altera Schematic Express utilities generate EDIF files for all files in the design.

Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the following sample Design Architect schematic files:

  • /usr/maxplus2/examples/mentor/example1/fulladd
  • /usr/maxplus2/examples/mentor/example3/fulladd2
  • /usr/maxplus2/examples/mentor/example7/fifo

Go to: Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.


Instantiating the clklock Megafunction in Design Architect Schematics

You can instantiate the Altera®­provided clklock phase-locked loop megafunction, which is supported for some FLEX® 10K devices, in a Design Architect schematic.

To instantiate the clklock megafunction in a Design Architect schematic, follow these steps:

  1. Choose Altera Libraries (Library menu).

  2. Choose ALTERA GENLIB (Altera Libraries menu).

  3. Choose clklock (ALTERA GENLIB menu).

  4. Specify appropriate values for the CLOCKBOOST and INPUT_FREQUENCY variables. Choose Megafunctions/LPM from the MAX+PLUS® II Help menu for detailed information on the clklock megafunction.

  5. Choose OK.

  6. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes clklock megafunction instantiation.

Go to: Go to FLEX 10K Device Family, which is available on the web, for additional information.


Instantiating LPM Functions in Design Architect Schematics

Design Architect software allows you to instantiate functions included in the library of parameterized modules (LPM) from the ALTERA LPMLIB library.

Go through the following steps to instantiate LPM functions in a Design Architect schematic:

  1. While you are entering your Design Architect schematic, choose Altera Libraries (Library menu).
  2. Choose ALTERA LPMLIB (Altera Libraries menu).
  3. Choose from the available LPM functions on the ALTERA GENLIB menu.
  4. In the LPM_<function name> dialog box, specify appropriate values for the variables displayed for the LPM function you chose in step 3. Make sure that any hexadecimal (Intel-format) file that you use to specify the initial content of a memory function does not have the same name as the design file name. Choose Megafunctions/LPM from the MAX+PLUS II Help menu for detailed information on LPM functions.
  5. Choose OK to generate a symbol for the LPM function you chose in step 3 and a corresponding VHDL simulation model.
  6. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.
  7. When you save the schematic, the Design Architect software will ask whether you want to compile the LPM model. Choose YES if you want to compile the VHDL code for the LPM functions. The software will automatically select the corresponding compiler: System 1076 for B.(x) releases and QuickHDL compilers for releases C.1 and later.

Installing the Altera®­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example7/fifo, which includes LPM instantiation.


Entering Resource Assignments

The MAX+PLUS® II software allows you to enter a variety of resource and device assignments for your projects. Resource assignments are used to assign logic functions to a particular pin, logic cell, I/O cell, embedded cell, row, column, Logic Array Block (LAB), Embedded Array Block (EAB), chip, clique, local routing, logic option, timing requirement, or connected pin group. In MAX+PLUS II software, you can enter all types of resource and device assignments with Assign menu commands. You can also enter pin, logic cell, I/O cell, embedded cell, LAB, EAB, row, and column assignments in the MAX+PLUS II Floorplan Editor. The Assign menu commands and the Floorplan Editor all save assignment information in the ASCII Assignment & Configuration File (.acf) for the project. In addition, you can edit ACFs manually in any standard text editor or with the setacf utility.

Design Architect Schematics

In Design Architect schematics, you can assign a limited subset of these resource assignments by assigning properties to symbols. These properties are incorporated into the EDIF netlist file(s). The MAX+PLUS II software automatically converts assignment information from the EDIF Input File into the ACF format. For information on making MAX+PLUS II-compatible resource assignments, go to the following topics:

  • Assigning Pins, Logic Cells & Chips
  • Assigning Cliques
  • Assigning Logic Options
  • Modifying the Assignment & Configuration File with the setacf Utility

Note: After you compile a project, you can back-annotate pin assignments, as described in Back­Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols.

Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample Design Architect schematic file /usr/maxplus2/examples/mentor/example4/fa2, which includes resource assignments.

VHDL & Verilog HDL Design Files

For Verilog HDL- and VHDL-based designs, you must use the MAX+PLUS II software or the setacf utility to enter resource assignments. Go to Modifying the Assignment & Configuration File with the setacf Utility for more information.

Go to: Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for more information on assignments or properties that can be assigned in Design Architect software. For information on entering assignments in MAX+PLUS II software with Assign menu commands or in an ACF, go to "resource assignments" or "ACF, format" in MAX+PLUS II Help using Search for Help on (Help menu).


Assigning Pins, Logic Cells & Chips

You can assign a single logic function to a specific pin or logic cell (including I/O cells and embedded cells) within a chip, and assign one or more functions to a specific chip. A chip is a group of logic functions defined as a single, named unit, which can be assigned to a specific device.

You can assign a signal to a particular pin to ensure that the signal is always associated with that pin, regardless of future changes to the project. If you wish to set and maintain the performance of your project, assigning logic to a specific logic cell within a chip can minimize timing delays. In a project that is partitioned among multiple devices, you can assign logic functions that must be kept together in the same device to a chip. Chip assignments allow you to split a project so that only a minimum number of signals travel between devices, and to ensure that no unnecessary device-to-device delays exist on critical timing paths. You can assign a chip to a device in some EDA tools or in the MAX+PLUS® II software.

Use the following syntax for chip, pin, and logic cell assignments:

  • To assign a logic function to a chip:

    CHIP_PIN_LC=<chip name>

    For example: CHIP_PIN_LC=chip1

  • To assign a pin number within a chip:

    CHIP_PIN_LC=<chip name>@<pin number>

    For example: CHIP_PIN_LC=chip1@K2

  • To assign a logic cell, I/O cell, or embedded cell number:

    CHIP_PIN_LC=<chip name>@LC<logic cell number>

    CHIP_PIN_LC=<chip name>@IOC<I/O cell number>

    CHIP_PIN_LC=<chip name>@EC<embedded cell number>

    For example: CHIP_PIN_LC=chip1@LC44

Note: Refer to the following sources for additional information:
  • Go to "Devices & Adapters" and "Assigning a Device" in MAX+PLUS II Help for information on device pin-outs and assigning devices, respectively, in the MAX+PLUS II software.
  • Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.


Assigning Cliques

You can define a group of logic functions as a single, named unit, called a clique. The MAX+PLUS® II Compiler attempts to place all logic in the clique in the same logic array block (LAB) to ensure optimum speed. If the project does not use multi-LAB devices, or if it is not possible to fit all clique members into a single LAB, the clique assignment ensures that all members of a clique are placed in the same device. In FLEX® 6000, FLEX 8000, FLEX 10K, and MAX® 9000 devices the Compiler also attempts to place the logic in LABs in the same row. Cliques therefore allow you to partition a project so that only a minimum number of signals travel between LABs, and to ensure that no unnecessary LAB-to-LAB or device-to-device delays exist on critical timing paths.

Step:

To assign a clique, use the following syntax:

CLIQUE=<clique name>

For example: CLIQUE=fast1

Go To:

Go to the following topics in MAX+PLUS II Help for related information:

  • Assigning a Clique
  • Guidelines for Achieving Maximum Speed Performance


Assigning Logic Options

Logic option and logic synthesis style assignments allow you to guide logic synthesis with logic optimization features that are specific to Altera® devices. You can assign logic options and styles to individual logic functions in your design. The MAX+PLUS® II Compiler also uses a device-family-specific default logic synthesis style for each project.

Note: Go to "Resource Assignments in EDIF Input Files" and "Assigning Resources in a Third-Party Design Editor" in MAX+PLUS II Help for complete and up-to-date information on logic option and logic synthesis style assignments, including definitions and syntax of these assignments.


Performing a Functional Simulation with DVE & QuickSim II Software

You can perform a functional simulation of a Design Architect schematic with the Mentor Graphics Design Viewpoint Editor (DVE) and QuickSim II software before compiling your project with the MAX+PLUS® II Compiler.

NOTE: If you wish to functionally simulate a hierarchical design that uses multiple design entry methods, you should use QuickHDL Pro rather than QuickSim. Refer to Performing a Functional Simulation with QuickHDL Pro Software for more information.

To functionally simulate a Design Architect schematic, go through the following steps:

  1. Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Mentor Graphics/Exemplar Logic Working Environment.
  2. Create a Design Architect schematic that follows the guidelines in Creating Design Architect Schematics for Use with MAX+PLUS II Software.
  3. In the Navigator window, select your project's folder, press Button 3, and choose Open max2_fve to start DVE. DVE checks the design and creates a viewpoint (called altera_fsim by default) for functional simulation with QuickSim II software.
  4. Select the altera_fsim icon, press Button 3, and choose Open max2_qsim from the Navigator window to start the QuickSim II software. You can also start the QuickSim II software by typing max2_qsim  at the UNIX prompt.
  5. Set the appropriate options and simulate your design.
  6. Use the ENWrite utility to generate an EDIF netlist file that can be imported into the MAX+PLUS II software, as described in Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility.
Go to: Go to Compiling Projects with MAX+PLUS II Software in these MAX+PLUS II ACCESSSM Key topics for related information.


Creating Hierarchical Projects with Design Architect Software

If you wish to create a hierarchical schematic design that contains symbols representing other design files, such as AHDL Text Design Files (.tdf), VHDL Design Files (.vhd), or Verilog Design Files (.v), you can create a hollow-body symbol for the design file and then instantiate it in your top-level design file.

To create a hollow-body symbol for a lower-level design file, follow these steps:

  1. (Optional) If you are creating a hollow-body symbol for a VHDL or Verilog HDL design file, you can first functionally simulate the VHDL or Verilog HDL file, as described in Performing a Functional Simulation with QuickHDL Software.
  2. Start the Design Architect software by double-clicking Button 1 on the max2_da icon in the Design Manager tools window. You can also start Design Architect software by typing max2_da  at the UNIX prompt.
  3. Choose the OPEN SYMBOL button in the Design Architect session_palette to open the Symbol Editor. Type the lower-level design file name, including the directory path, in the Component Name box. Choose OK.
  4. Create a symbol that represents the inputs and outputs of the lower-level file.
  5. Assign PINTYPE properties of IN or OUT to the inputs and outputs of the symbol, and assign appropriate values to any other properties of the symbol so that it can be identified in the top-level schematic.
  6. Go to: If you are creating a hollow-body symbol for a VHDL design file, be sure to assign the value qvpro to the symbol's model property so that it can be identified as a VHDL component in the top-level schematic.

  7. Check and save the symbol, then close the Symbol Editor.
  8. To enter the symbol, choose the CHOOSE SYMBOL button from the Design Architect session_palette.
  9. Select the symbol file from the Navigator menu and choose OK.
  10. The MAX+PLUS® II software uses the Altera®­provided mnt8_bas.lmf Library Mapping File to map Design Architect symbols to equivalent MAX+PLUS II logic functions. To use custom symbols, you must create a custom LMF that maps your custom symbols to the equivalent EDIF Input File, Text Design File (TDF), or other design file. You will also need to specify this LMF in the EDIF Netlist Reader Settings dialog box before compiling the design with the MAX+PLUS II software. See Compiling Projects with MAX+PLUS II Software for more information.
  11. Continue with the steps necessary to complete your Design Architect schematic, as described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.

Installing the Altera­provided MAX+PLUS II/Mentor Graphics/Exemplar Logic interface on your computer automatically creates the sample hierarchical Design Architect schematic file /usr/maxplus2/examples/mentor/example3/fulladd2.


Converting Design Architect Schematics into MAX+PLUS II-Compatible EDIF Netlist Files with the ENWrite Utility

After you have created a Design Architect schematic or a hierarchical schematic design that uses multiple design entry methods, you can use the Mentor Graphics ENWrite utility to convert it into an EDIF netlist file that can be processed with the MAX+PLUS® II software.

To generate an EDIF netlist file for use with the MAX+PLUS II Compiler, go through the following steps:

  1. Create a Design Architect Schematic that follows the guidelines described in Creating Design Architect Schematics for Use with MAX+PLUS II Software.
  2. Select the folder for your project, press Button 3, and choose Open max2_enw from the Navigator window to open Design Viewpoint Editor (DVE), then ENWrite. You can also start the ENWrite utility by typing max2_enw  at the UNIX prompt.
  3. Choose OK in the $invoke_enw dialog box to accept the default names for the DVE viewpoint altera_edif, which is used internally by ENWrite, and the ENWrite hierarchical EDIF netlist file <design name>.edf. Specify OFF for the port array construct in the EDIF netlist file.
  4. Note: The MAX+PLUS II software supports bus constructs in EDIF 2 0 0 and 3 0 0 netlist files, which allow you to retain any bus structures in your design. To preserve a bus in the EDIF netlist file, turn on the port array construct option in the $invoke_enw dialog box. However, if your design contains library of parameterized modules (LPM) functions, you should not use this feature because LPM 2.0.1 and 2.1.0 functions do not support EDIF bus constructs.

    After DVE checks the Design Architect schematic, ENWrite generates <design name>.edf and automatically copies it to your project's directory.

  5. Compile the resulting EDIF netlist file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.


Compiling Projects with MAX+PLUS II Software

The MAX+PLUS® II Compiler can process design files in a variety of formats. This topic describes how to use MAX+PLUS II software to compile projects in which the top-level design file is an EDIF Input File (with the extension .edf).

Note: Refer to the following sources for additional information:

  • Go to MAX+PLUS II Help for information on compiling VHDL and Verilog HDL, design files directly with the MAX+PLUS II Compiler.

  • Go to Running Synopsys Compilers from MAX+PLUS II Software for information on running the Synopsys Design Compiler or FPGA Compiler software on a VHDL or Verilog HDL design from within the MAX+PLUS II Compiler window.

To compile a design (also called a "project") with MAX+PLUS II software, go through the following steps:

  1. Create design files that are compatible with the MAX+PLUS II software and convert them into EDIF Input Files with the extension .edf. Specific instructions for some tools are described in these MAX+PLUS II ACCESSSM Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your design entry or synthesis and optimization tool.

  2. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, create a mapping for each function in a Library Mapping File (.lmf) to map the custom symbol to the corresponding EDIF Input File, AHDL Text Design File (.tdf), or other MAX+PLUS II-supported design file. These custom functions are represented in design files as hollow-body symbols or "black box" HDL descriptions.

    Note: Go to "Library Mapping Files (.lmf)" in MAX+PLUS II Help for more information.

  3. Open MAX+PLUS II and specify the name of your top-level design file as the project name with the Project Name command (File menu). If you open an HDL file in the MAX+PLUS II Text Editor, you can choose the Project Set Project to Current File command (File menu) instead.

    Note: You can also compile a project from a command line. However, the first time you compile a project, the settings you need to specify are easier to specify from within the MAX+PLUS II software. After you have run the graphical user interface for the MAX+PLUS II software at least once, you can more easily use the command-line setacf utility to modify options in the Assignment & Configuration File (.acf) for the project. Type setacf -h Enter and maxplus2 -h Enter for descriptions of setacf and MAX+PLUS II command-line syntax.

  4. Choose Device (Assign menu) and select the target Altera device family in the Device Family drop-down list box. If you wish to implement the design logic in a specific device, select it in the Devices box. Otherwise, select AUTO to allow the MAX+PLUS II Compiler to choose the best device(s) in the current device family. If your design entry or synthesis and optimization tool required you to specify a target family and/or device, specify the same information in this dialog box. For information on partitioning logic among multiple devices, go to MAX+PLUS II Help. Choose OK.

  5. Open the Compiler window by choosing the Compiler command (MAX+PLUS II menu). Go through the following steps to specify the options necessary to compile the design file(s) in your project:

    1. Ensure that all EDIF netlist files have the extension .edf and choose EDIF Netlist Reader Settings (Interfaces menu).

    2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor. This name should be the name of the vendor whose tool(s) you used to create the EDIF netlist files. If your vendor name does not appear, select Custom instead.

      Note: If you are compiling a design created with Synopsys FPGA Express software, select Synopsys, choose the Customize button, enter <project name>.lmf in the LMF #1 box, choose OK, and skip to step 6.

    3. If you selected an existing vendor name in the Vendor box and your project contains design files that require custom LMF mappings, choose the Customize button to expand the dialog box to show all settings. Turn on the LMF #2 checkbox and type your custom LMF's filename in the corresponding text box, or select a name from the Files box. The selection in the Vendor box will change to Custom and all settings will be retained until you change them again.

    4. If you selected Custom in the Vendor box, choose the Customize button to expand the dialog box to show all settings. Any previously defined custom settings will be displayed. Under Signal Names, type one or more names with up to 20 total name characters in the VCC or GND box if your EDIF Input File(s) use one or more names other than VCC or GND for the global high or low signals. Multiple signal names must be separated by either a comma (,) or a space. Under Library Mapping Files, turn on the LMF #1 checkbox and type a filename in the text box following it, or select a name from the Files box. If necessary, specify another LMF name in the LMF #2 box. Go to MAX+PLUS II Help for detailed information on the settings available in the EDIF Netlist Reader Settings dialog box.

    5. Choose OK.

  6. If your design files contain symbols (or HDL instantiations) representing your own custom lower-level logic functions, you may need to ensure that all files are present in your project directory, i.e., the same directory as the top-level design file. Otherwise, you must specify the directories containing these files as user libraries with the User Libraries command (Options menu).

  7. Follow all guidelines that apply to your design entry or synthesis and optimization tool:

    • Exemplar Logic Galileo Extreme-Specific Compiler Settings
    • Synopsys DesignWare-Specific Compiler Settings
    • Converting Synopsys FPGA Compiler & Design Compiler Timing Constraints into MAX+PLUS II-Compatible Format with the syn2acf Utility
    • Synplicity Synplify-Specific Compiler Settings

  8. If you wish to generate EDIF, VHDL, or Verilog HDL output files for post-compilation simulation or timing analysis with another EDA tool, go through the following steps:

    1. (Optional) Turn on the Optimize Timing SNF command (Processing menu) to reduce the size of the output file(s). Turning on this command can reduce the size of output netlists by up to 30%.

      Note: This command does not create optimized timing SNFs on UNIX workstations. However, a non-optimized timing SNF provides the same functional and timing information as an optimized timing SNF.

    2. If you wish to generate EDIF Output Files (.edo), go through these steps:

      1. Turn on the EDIF Netlist Writer command (Interfaces menu). Then choose the EDIF Netlist Writer Settings command (Interfaces menu).

      2. Select a vendor name in the Vendor drop-down list box to activate the default settings for that vendor and choose OK. If your vendor name does not appear, select Custom instead and specify the settings that are appropriate for your simulation or timing analysis tool. Go to MAX+PLUS II Help for detailed information on the options available in the EDIF Netlist Writer Settings dialog box.

      3. To generate an optional Standard Delay Format (SDF) Output File (.sdo), choose the Customize button to expand the dialog box to show all settings. Select one of the SDF Output File options under Write Delay Constructs To, and choose OK.

      The filenames of the EDIF Output File(s) and optional SDF Output File(s) are the same as the user-defined chip name(s) for the project; if no chip names exist, the Compiler assigns filenames that are based on the project name. For a multi-device project, the Compiler also generates a top-level EDIF Output File that is uniquely identified by "_t" appended to the project name. In addition, the Compiler automatically generates a VHDL Memory Model Output File, <project name>.vmo, when it generates an EDIF Output File that contains memory (RAM or ROM).

    3. If you wish to generate VHDL Output Files (.vho), turn on the VHDL Netlist Writer command (Interfaces menu). Then choose VHDL Netlist Writer Settings command (Interfaces menu). Select VHDL Output File (.vho) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF ver. 2.1 files contain timing delay information that allows you to perform back-annotation simulation in VHDL with VITAL-compliant simulation libraries. The VHDL Output Files generated by the Compiler have the extension .vho, but are otherwise named in the same way as the EDIF Output Files described above.

    4. If you wish to generate Verilog HDL Output Files (.vo), turn on the Verilog Netlist Writer command (Interfaces menu). Then choose Verilog Netlist Writer Settings command (Interfaces menu). Select Verilog Output File (.vo) or one of the SDF Output File options under Write Delay Constructs To, and choose OK. SDF Output Files contain timing delay information that allows you to perform back-annotation simulation in Verilog HDL. The Verilog Output Files generated by the Compiler have the extension .vo, but are otherwise named in the same way as the EDIF Output Files described above.

  9. To run the MAX+PLUS II Compiler, choose the Project Save & Compile command (File menu) or choose the Start button in the Compiler window.

    Note: See step 3 for information on running MAX+PLUS II software from the command line.

  10. Once you have compiled the project with the MAX+PLUS II Compiler, you can use the VHDL, Verilog HDL, or EDIF output file(s), and the optional SDF Output File(s) (.sdo) to perform timing analysis or timing simulation with another EDA tool. Specific instructions for some tools are described in these MAX+PLUS II ACCESS Key Guidelines. Otherwise, refer to MAX+PLUS II Help or the product documentation for your EDA tool.

The MAX+PLUS II Compiler also generates a Report File (.rpt), a Pin-Out File (.pin), and one or more of the following files for device programming or configuration:

  • JEDEC Files (.jed)
  • Programmer Object Files (.pof)
  • SRAM Object Files (.sof)
  • Hexadecimal (Intel-format) Files (.hex)
  • Tabular Text Files (.ttf)
Go to: Refer to the following sources for additional information:
  • Go to Compiler Procedures in MAX+PLUS II Help for information on other available Compiler settings.
  • Go to Programmer Procedures in MAX+PLUS II Help for instructions on creating other types of programming files and on programming or configuring Altera devices.
  • Go to Back-Annotating MAX+PLUS II Pin Assignments to Design Architect Symbols for information on back-annotating pin assignments in Mentor Graphics Design Architect schematics.
  • Go to Programming Altera Devices for information on the different programming hardware options for Altera device families.

 

Go to the following topics, which are available on the web, for additional information:

  • MAX+PLUS II Development Software
  • Altera Programming Hardware

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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