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Instantiating the clklock Megafunction in VHDL & Verilog HDL Designs

Altera provides the gencklk utility to allow you to instantiate clklock (phase­locked loop) functions in Mentor Graphics/Exemplar Logic software. The gencklk utility appends the parameter values to the clklock function name, so you don't need to declare attributes explicitly. The naming rule for the clklock function is clklock_<ClockBoost>_<inputfrequency>. The gencklk utility has the following syntax:

gencklk <ClockBoost> <inputfrequency> [­vhdl] [­verilog] Enter

For the <ClockBoost> variable, you should specify a ClockBoost value of 1 or 2 (default value is 1). For the <inputfrequency> variable, you should specify a decimal value in MHz (default value is 50). To generate a VHDL file (which is the default if no option is present), specify ­vhdl; to generate a Verilog HDL file, specify ­verilog.

For example, to create the VHDL file clklock_2_50.vhd and the corresponding Component Declaration file clklock_2_50.cmp, type the following command at the UNIX prompt:

gencklk 2 50 -vhdl Enter

Installing the Altera­provided MAX+PLUS II/Mentor Graphics interface on your computer automatically creates the sample VHDL design file /usr/maxplus2/examples/mentor/example6/count8.vhd, which includes clklock megafunction instantiation.

Last Updated: August 28, 2000 for MAX+PLUS II version 10.0
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