Synthesizing & Optimizing VHDL Designs with ViewSynthesis Software |
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You can create and process VHDL files and convert them into Altera® Hardware Description Language (AHDL) Text Design Files (.tdf) or EDIF Input Files (.edf) that can be processed by the MAX+PLUS® II Compiler. The MAX+PLUS II Compiler can process a VHDL file that has been synthesized by ViewSynthesis software, saved as an AHDL TDF or an EDIF netlist file, and imported into the MAX+PLUS II software. The information presented here describes only how to use VHDL files that have been processed by ViewSynthesis software. For information on direct MAX+PLUS II support for VHDL Design Files, go to MAX+PLUS II VHDL Help.
To synthesize and optimize a VHDL design, follow these steps:
- Be sure to set up your working environment correctly, as described in Setting Up the MAX+PLUS II/Viewlogic Powerview Working Environment.
- Create a VHDL file <design name>.vhd using the MAX+PLUS II Text Editor or another standard text editor and save it in a working directory. Go to Creating VHDL Designs for Use with MAX+PLUS II Software for more information.
- Start Powerview by typing
powerview at a UNIX prompt.
- In the Cockpit window, select Altera in the Current ToolBox drop-down list box, and select the drawer you want to use, i.e., Design Tools or Max2 Express, in the Current Drawer drop-down list box.
- Choose Create (Project menu) from your working directory to create your project directory. Choose OK.
- Choose SearchOrder (Project menu) to add the appropriate library directories and aliases to your viewdraw.ini file. Refer to Viewlogic Powerview viewdraw.ini Configuration File for more information on Powerview application libraries.
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When you add libraries to the /usr/maxplus2/vwlogic/standard/viewdraw.ini file, they are automatically set when you create a new project. Powerview tools search these libraries sequentially, so it is important to add them in the order in which they are listed. |
- Analyze the VHDL design, as described in Analyzing VHDL Files with the Vantage VHDL Analyzer Software.
- (Optional) Perform a functional simulation, as described in Performing a Timing Simulation with ViewSim Software.
- In Powerview 5.3.2 and previous versions, start ViewSynthesis software by double-clicking Button 1 on the max2_syn icon in the Altera Toolbox Design Tools Drawer.
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In Powerview 6.0, ViewSynthesis software is available only for the SunOS, and only as a command-line version. If you are using Powerview 6.0, read /<Powerview system directory>/README/vsyn.doc to learn how to synthesize a design with ViewSynthesis software. You can create the synth.ini file, a one-line text file that contains the text technology altera. Then type the following commands at the UNIX prompt to analyze and synthesize your VHDL design:
vsyn -vhdl <design name>
vsyn -synth "*" 
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- Choose Target Technology (Setup menu) and select altera:altera in the Specify Target Technology dialog box. Choose OK.
- Choose Compile VHDL (Setup menu) and select <design name>.vhd in the VHDL Files list box. Choose OK.
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If more than one VHDL Design File (.vhd) exists for the project, you must compile the lower-level design files before compiling the top-level file. |
- Press Button 3 on the <design name> icon in the ViewSynthesis window, choose Synthesize from the pop-up menu, then choose OK.
- (Optional) To generate a synthesis report file for the design, press Button 3 on the <design name> icon and choose View Report from the pop-up menu.
- (Optional) To create a schematic representation of the gate-level netlist file, press Button 3 on the <design name> icon and choose View Schematic from the pop-up menu.
- Generate an EDIF netlist file that can be compiled with the MAX+PLUS II Compiler, as described in Converting ViewDraw Schematics or VHDL Designs into MAX+PLUS II-Compatible EDIF Netlist Files with the edifneto Utility.
- Process the <design name>.edf file with the MAX+PLUS II Compiler, as described in Compiling Projects with MAX+PLUS II Software.
Installing the Altera-provided MAX+PLUS II/Viewlogic interface on your computer automatically creates the following sample ViewDraw schematic files:
- /usr/maxplus2/examples/viewlogic/example5/count4.vhd
- /usr/maxplus2/examples/viewlogic/example5/count8.vhd
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